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tcti: remove TCTI backend

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This commit is contained in:
osy
2024-09-27 16:23:13 -07:00
parent af8e401723
commit dbdc0ed819
17 changed files with 13 additions and 4782 deletions
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accel/tcg/tcg-accel-ops.c
-5
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@@ -62,11 +62,6 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
cflags |= parallel ? CF_PARALLEL : 0;
cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
#if defined(CONFIG_TCG_THREADED_INTERPRETER)
// GOTO_PTR is too complex to emit a simple gadget for.
// We'll let C handle it, since the overhead is similar.
cflags |= CF_NO_GOTO_PTR;
#endif
tcg_cflags_set(cpu, cflags);
}
include/disas/dis-asm.h
-1
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@@ -416,7 +416,6 @@ typedef struct disassemble_info {
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
int print_insn_tci(bfd_vma, disassemble_info*);
int print_insn_tcti(bfd_vma, disassemble_info*);
int print_insn_big_mips (bfd_vma, disassemble_info*);
int print_insn_little_mips (bfd_vma, disassemble_info*);
int print_insn_nanomips (bfd_vma, disassemble_info*);
include/exec/exec-all.h
-4
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@@ -457,11 +457,7 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
#if defined(CONFIG_TCG_INTERPRETER)
extern __thread uintptr_t tci_tb_ptr;
# define GETPC() tci_tb_ptr
#elif defined(CONFIG_TCG_THREADED_INTERPRETER)
extern __thread uintptr_t tcti_call_return_address;
# define GETPC() tcti_call_return_address
#else
/* Note that this is correct for TCTI also; whose gadget behaves like native code. */
# define GETPC() \
((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
#endif
include/tcg/tcg-opc.h
-4
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@@ -195,11 +195,7 @@ DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT)
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
#if defined(CONFIG_TCG_THREADED_INTERPRETER)
DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
#else
DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
#endif
DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT)
include/tcg/tcg.h
+1 -1
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@@ -1024,7 +1024,7 @@ static inline size_t tcg_current_code_size(TCGContext *s)
#define TB_EXIT_IDXMAX 1
#define TB_EXIT_REQUESTED 3
#if defined(CONFIG_TCG_INTERPRETER) || defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifdef CONFIG_TCG_INTERPRETER
uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr);
#else
typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr);
meson.build
-93
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@@ -47,7 +47,6 @@ bsd_oses = ['gnu/kfreebsd', 'freebsd', 'netbsd', 'openbsd', 'dragonfly', 'darwin
supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux']
supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64',
'arm', 'aarch64', 'loongarch64', 'mips', 'mips64', 'sparc64']
tcti_supported_cpus = ['aarch64']
cpu = host_machine.cpu_family()
@@ -817,8 +816,6 @@ if host_os == 'netbsd'
endif
endif
tcti_gadgets = files()
tcg_arch = host_arch
if get_option('tcg').allowed()
if host_arch == 'unknown'
@@ -835,87 +832,6 @@ if get_option('tcg').allowed()
endif
if get_option('tcg_interpreter')
tcg_arch = 'tci'
elif get_option('tcg_threaded_interpreter')
if cpu not in tcti_supported_cpus
error('Unsupported CPU @0@ for TCTI, try --enable-tcg-interpreter'.format(cpu))
else
warning('TCTI is extremely experimental and incomplete! Things might break!')
tcg_arch = '@0@-tcti'.format(cpu)
endif
# Tell our compiler how to generate our TCTI gadgets.
gadget_generator = 'tcg/@0@/tcti-gadget-gen.py'.format(tcg_arch)
tcti_sources = [
'tcti_gadgets.h',
'tcti_misc_gadgets.c',
'tcti_misc_gadgets.h',
'tcti_setcond_gadgets.c',
'tcti_setcond_gadgets.h',
'tcti_brcond_gadgets.c',
'tcti_brcond_gadgets.h',
'tcti_mov_gadgets.c',
'tcti_mov_gadgets.h',
'tcti_load_signed_gadgets.c',
'tcti_load_signed_gadgets.h',
'tcti_load_unsigned_gadgets.c',
'tcti_load_unsigned_gadgets.h',
'tcti_store_gadgets.c',
'tcti_store_gadgets.h',
'tcti_arithmetic_gadgets.c',
'tcti_arithmetic_gadgets.h',
'tcti_logical_gadgets.c',
'tcti_logical_gadgets.h',
'tcti_extension_gadgets.c',
'tcti_extension_gadgets.h',
'tcti_bitwise_gadgets.c',
'tcti_bitwise_gadgets.h',
'tcti_byteswap_gadgets.c',
'tcti_byteswap_gadgets.h',
'tcti_qemu_ld_aligned_signed_le_gadgets.c',
'tcti_qemu_ld_aligned_signed_le_gadgets.h',
'tcti_qemu_ld_unaligned_signed_le_gadgets.c',
'tcti_qemu_ld_unaligned_signed_le_gadgets.h',
'tcti_qemu_ld_slowpath_signed_le_gadgets.c',
'tcti_qemu_ld_slowpath_signed_le_gadgets.h',
'tcti_qemu_ld_aligned_unsigned_le_gadgets.c',
'tcti_qemu_ld_aligned_unsigned_le_gadgets.h',
'tcti_qemu_ld_unaligned_unsigned_le_gadgets.c',
'tcti_qemu_ld_unaligned_unsigned_le_gadgets.h',
'tcti_qemu_ld_slowpath_unsigned_le_gadgets.c',
'tcti_qemu_ld_slowpath_unsigned_le_gadgets.h',
'tcti_qemu_ld_aligned_be_gadgets.c',
'tcti_qemu_ld_aligned_be_gadgets.h',
'tcti_qemu_ld_unaligned_be_gadgets.c',
'tcti_qemu_ld_unaligned_be_gadgets.h',
'tcti_qemu_ld_slowpath_be_gadgets.c',
'tcti_qemu_ld_slowpath_be_gadgets.h',
'tcti_qemu_st_aligned_le_gadgets.c',
'tcti_qemu_st_aligned_le_gadgets.h',
'tcti_qemu_st_unaligned_le_gadgets.c',
'tcti_qemu_st_unaligned_le_gadgets.h',
'tcti_qemu_st_slowpath_le_gadgets.c',
'tcti_qemu_st_slowpath_le_gadgets.h',
'tcti_qemu_st_aligned_be_gadgets.c',
'tcti_qemu_st_aligned_be_gadgets.h',
'tcti_qemu_st_unaligned_be_gadgets.c',
'tcti_qemu_st_unaligned_be_gadgets.h',
'tcti_qemu_st_slowpath_be_gadgets.c',
'tcti_qemu_st_slowpath_be_gadgets.h',
'tcti_simd_base_gadgets.c',
'tcti_simd_base_gadgets.h',
'tcti_simd_arithmetic_gadgets.c',
'tcti_simd_arithmetic_gadgets.h',
'tcti_simd_logical_gadgets.c',
'tcti_simd_logical_gadgets.h',
'tcti_simd_immediate_gadgets.c',
'tcti_simd_immediate_gadgets.h',
]
tcti_gadgets = custom_target('tcti-gadgets.h',
output: tcti_sources,
input: gadget_generator,
command: [find_program(gadget_generator)],
build_by_default: true,
build_always_stale: false)
elif host_arch == 'x86_64'
tcg_arch = 'i386'
elif host_arch == 'ppc64'
@@ -2475,7 +2391,6 @@ config_host_data.set('CONFIG_SOLARIS', host_os == 'sunos')
if get_option('tcg').allowed()
config_host_data.set('CONFIG_TCG', 1)
config_host_data.set('CONFIG_TCG_INTERPRETER', tcg_arch == 'tci')
config_host_data.set('CONFIG_TCG_THREADED_INTERPRETER', tcg_arch.endswith('tcti'))
endif
config_host_data.set('CONFIG_TPM', have_tpm)
config_host_data.set('CONFIG_TSAN', get_option('tsan'))
@@ -3722,12 +3637,6 @@ endif
common_ss.add(pagevary)
specific_ss.add(files('page-target.c', 'page-vary-target.c'))
# FIXME: This is being used for now for development quickness, but these realy should be
# added to a gadget-specific shared library (tcti_ss).
if get_option('tcg').allowed() and tcg_arch.endswith('tcti')
specific_ss.add(tcti_gadgets)
endif
subdir('backends')
subdir('disas')
subdir('migration')
@@ -4519,8 +4428,6 @@ summary_info += {'TCG support': config_all_accel.has_key('CONFIG_TCG')}
if config_all_accel.has_key('CONFIG_TCG')
if get_option('tcg_interpreter')
summary_info += {'TCG backend': 'TCI (TCG with bytecode interpreter, slow)'}
elif get_option('tcg_threaded_interpreter')
summary_info += {'TCG backend': 'TCTI (TCG with threaded-dispatch bytecode interpreter, experimental and slow; but faster than TCI)'}
else
summary_info += {'TCG backend': 'native (@0@)'.format(cpu)}
endif
meson_options.txt
-2
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@@ -93,8 +93,6 @@ option('debug_remap', type: 'boolean', value: false,
description: 'syscall buffer debugging support')
option('tcg_interpreter', type: 'boolean', value: false,
description: 'TCG with bytecode interpreter (slow)')
option('tcg_threaded_interpreter', type: 'boolean', value: false,
description: 'TCG with threaded-dispatch bytecode interpreter (experimental and slow, but less slow than TCI)')
option('safe_stack', type: 'boolean', value: false,
description: 'SafeStack Stack Smash Protection (requires clang/llvm and coroutine backend ucontext)')
option('sanitizers', type: 'boolean', value: false,
scripts/meson-buildoptions.sh
+2 -7
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@@ -51,9 +51,6 @@ meson_options_help() {
printf "%s\n" ' --enable-shared-lib Build QEMU as a shared library'
printf "%s\n" ' --enable-strip Strip targets on install'
printf "%s\n" ' --enable-tcg-interpreter TCG with bytecode interpreter (slow)'
printf "%s\n" ' --enable-tcg-threaded-interpreter'
printf "%s\n" ' TCG with threaded-dispatch bytecode interpreter'
printf "%s\n" ' (experimental and slow, but less slow than TCI)'
printf "%s\n" ' --enable-trace-backends=CHOICES'
printf "%s\n" ' Set available tracing backends [log] (choices:'
printf "%s\n" ' dtrace/ftrace/log/nop/simple/syslog/ust)'
@@ -67,9 +64,9 @@ meson_options_help() {
printf "%s\n" ' --libdir=VALUE Library directory [system default]'
printf "%s\n" ' --libexecdir=VALUE Library executable directory [libexec]'
printf "%s\n" ' --localedir=VALUE Locale data directory [share/locale]'
printf "%s\n" ' --localstatedir=VALUE Localstate data directory [var]'
printf "%s\n" ' --localstatedir=VALUE Localstate data directory [/var/local]'
printf "%s\n" ' --mandir=VALUE Manual page directory [share/man]'
printf "%s\n" ' --prefix=VALUE Installation prefix [/opt/homebrew]'
printf "%s\n" ' --prefix=VALUE Installation prefix [/usr/local]'
printf "%s\n" ' --qemu-ga-distro=VALUE second path element in qemu-ga registry entries'
printf "%s\n" ' [Linux]'
printf "%s\n" ' --qemu-ga-manufacturer=VALUE'
@@ -502,8 +499,6 @@ _meson_option_parse() {
--disable-tcg) printf "%s" -Dtcg=disabled ;;
--enable-tcg-interpreter) printf "%s" -Dtcg_interpreter=true ;;
--disable-tcg-interpreter) printf "%s" -Dtcg_interpreter=false ;;
--enable-tcg-threaded-interpreter) printf "%s" -Dtcg_threaded_interpreter=true ;;
--disable-tcg-threaded-interpreter) printf "%s" -Dtcg_threaded_interpreter=false ;;
--tls-priority=*) quote_sh "-Dtls_priority=$2" ;;
--enable-tools) printf "%s" -Dtools=enabled ;;
--disable-tools) printf "%s" -Dtools=disabled ;;
tcg/aarch64-tcti/README.md
-1026
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File diff suppressed because it is too large Load Diff
tcg/aarch64-tcti/tcg-target-con-set.h
-32
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@@ -1,32 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* TCI target-specific constraint sets.
* Copyright (c) 2021 Linaro
*/
/*
* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
* Each operand should be a sequence of constraint letters as defined by
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
// Simple register functions.
C_O0_I1(r)
C_O0_I2(r, r)
C_O0_I3(r, r, r)
//C_O0_I4(r, r, r, r)
C_O1_I1(r, r)
C_O1_I2(r, r, r)
//C_O1_I4(r, r, r, r, r)
//C_O2_I1(r, r, r)
//C_O2_I2(r, r, r, r)
//C_O2_I4(r, r, r, r, r, r)
// Vector functions.
C_O1_I1(w, w)
C_O1_I1(w, r)
C_O0_I2(w, r)
C_O1_I1(w, wr)
C_O1_I2(w, w, w)
C_O1_I3(w, w, w, w)
C_O1_I2(w, 0, w)
tcg/aarch64-tcti/tcg-target-con-str.h
-20
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@@ -1,20 +0,0 @@
/* SPDX-License-Identifier: MIT */
/*
* Define TCI target-specific operand constraints.
* Copyright (c) 2021 Linaro
*/
/*
* Define constraint letters for register sets:
* REGS(letter, register_mask)
*/
REGS('r', TCG_MASK_GP_REGISTERS)
REGS('w', TCG_MASK_VECTOR_REGISTERS)
/*
* Define constraint letters for constants:
* CONST(letter, TCG_CT_CONST_* bit set)
*/
// Simple 64-bit immediates.
CONST('I', 0xFFFFFFFFFFFFFFFF)
tcg/aarch64-tcti/tcg-target.c.inc
-2141
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File diff suppressed because it is too large Load Diff
tcg/aarch64-tcti/tcg-target.h
-254
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@@ -1,254 +0,0 @@
/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2009, 2011 Stefan Weil
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/*
* This code implements a TCG which does not generate machine code for some
* real target machine but which generates virtual machine code for an
* interpreter. Interpreted pseudo code is slow, but it works on any host.
*
* Some remarks might help in understanding the code:
*
* "target" or "TCG target" is the machine which runs the generated code.
* This is different to the usual meaning in QEMU where "target" is the
* emulated machine. So normally QEMU host is identical to TCG target.
* Here the TCG target is a virtual machine, but this virtual machine must
* use the same word size like the real machine.
* Therefore, we need both 32 and 64 bit virtual machines (interpreter).
*/
#ifndef TCG_TARGET_H
#define TCG_TARGET_H
#if UINTPTR_MAX == UINT32_MAX
# error We only support AArch64 running in 64B mode.
#elif UINTPTR_MAX == UINT64_MAX
# define TCG_TARGET_REG_BITS 64
#else
# error Unknown pointer size for tcti target
#endif
#define TCG_TARGET_INSN_UNIT_SIZE 1
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
// We're an interpreted target; even if we're JIT-compiling to our interpreter's
// weird psuedo-native bytecode. We'll indicate that we're intepreted.
#define TCG_TARGET_INTERPRETER 1
//
// Supported optional scalar instructions.
//
// Divs.
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
// Extends.
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
// Register extractions.
#define TCG_TARGET_HAS_extrl_i64_i32 1
#define TCG_TARGET_HAS_extrh_i64_i32 1
// Negations.
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_not_i64 1
// Logicals.
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_nand_i64 1
// Bitwise operations.
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1
#define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1
// Swaps.
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
//
// Supported optional vector instructions.
//
#define TCG_TARGET_HAS_v64 1
#define TCG_TARGET_HAS_v128 1
#define TCG_TARGET_HAS_v256 0
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 1
#define TCG_TARGET_HAS_nand_vec 0
#define TCG_TARGET_HAS_nor_vec 0
#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
//
// Unsupported instructions.
//
// There's no direct instruction with which to count the number of ones,
// so we'll leave this implemented as other instructions.
#define TCG_TARGET_HAS_ctpop_i32 0
#define TCG_TARGET_HAS_ctpop_i64 0
// We don't currently support gadgets with more than three arguments,
// so we can't yet create movcond, deposit, or extract gadgets.
#define TCG_TARGET_HAS_movcond_i32 0
#define TCG_TARGET_HAS_movcond_i64 0
#define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
// This operation exists specifically to allow us to provide differing register
// constraints for 8-bit loads and stores. We don't need to do so, so we'll leave
// this unimplemented, as we gain nothing by it.
#define TCG_TARGET_HAS_qemu_st8_i32 0
// These should always be zero on our 64B platform.
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_extract2_i64 0
//
// Platform metadata.
//
// Number of registers available.
#define TCG_TARGET_NB_REGS 64
// Number of general purpose registers.
#define TCG_TARGET_GP_REGS 16
/* List of registers which are used by TCG. */
typedef enum {
// General purpose registers.
// Note that we name every _host_ register here; but don't
// necessarily use them; that's determined by the allocation order
// and the number of registers setting above. These just give us the ability
// to refer to these by name.
TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,
TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7,
TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11,
TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15,
TCG_REG_R16, TCG_REG_R17, TCG_REG_R18, TCG_REG_R19,
TCG_REG_R20, TCG_REG_R21, TCG_REG_R22, TCG_REG_R23,
TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
// Register aliases.
TCG_AREG0 = TCG_REG_R14,
TCG_REG_CALL_STACK = TCG_REG_R15,
// Mask that refers to the GP registers.
TCG_MASK_GP_REGISTERS = 0xFFFFul,
// Vector registers.
TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
// Mask that refers to the vector registers.
TCG_MASK_VECTOR_REGISTERS = 0xFFFF000000000000ul,
} TCGReg;
// Specify the shape of the stack our runtime will use.
#define TCG_TARGET_CALL_STACK_OFFSET 0
#define TCG_TARGET_STACK_ALIGN 16
#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
// We're interpreted, so we'll use our own code to run TB_EXEC.
#define HAVE_TCG_QEMU_TB_EXEC
// We'll need to enforce memory ordering with barriers.
#define TCG_TARGET_DEFAULT_MO (0)
void tci_disas(uint8_t opc);
#endif /* TCG_TARGET_H */
tcg/aarch64-tcti/tcg-target.opc.h
-14
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@@ -1,14 +0,0 @@
/*
* Copyright (c) 2019 Linaro
*
* This work is licensed under the terms of the GNU GPL, version 2 or
* (at your option) any later version.
*
* See the COPYING file in the top-level directory for details.
*
* Target-specific opcodes for host vector expansion. These will be
* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
* consider these to be UNSPEC with names.
*/
DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC)
tcg/aarch64-tcti/tcti-gadget-gen.py
-1163
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File diff suppressed because it is too large Load Diff
tcg/region.c
+4 -4
View File
@@ -568,7 +568,7 @@ static int alloc_code_gen_buffer_anon(size_t size, int prot,
return prot;
}
#if !defined(CONFIG_TCG_INTERPRETER) && !defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifndef CONFIG_TCG_INTERPRETER
#ifdef CONFIG_POSIX
#include "qemu/memfd.h"
@@ -670,7 +670,7 @@ static int alloc_code_gen_buffer_splitwx_vmremap(size_t size, Error **errp)
static int alloc_code_gen_buffer_splitwx(size_t size, Error **errp)
{
#if !defined(CONFIG_TCG_INTERPRETER) && !defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifndef CONFIG_TCG_INTERPRETER
# ifdef CONFIG_DARWIN
return alloc_code_gen_buffer_splitwx_vmremap(size, errp);
# endif
@@ -710,7 +710,7 @@ static int alloc_code_gen_buffer(size_t size, int splitwx, Error **errp)
*/
prot = PROT_NONE;
flags = MAP_PRIVATE | MAP_ANONYMOUS;
#if defined(CONFIG_TCG_INTERPRETER) || defined(CONFIG_TCG_THREADED_INTERPRETER)
#if defined(CONFIG_TCG_INTERPRETER)
/* The tcg interpreter does not need execute permission. */
prot = PROT_READ | PROT_WRITE;
#elif defined(CONFIG_DARWIN)
@@ -819,7 +819,7 @@ void tcg_region_init(size_t tb_size, int splitwx, unsigned max_cpus)
* Work with the page protections set up with the initial mapping.
*/
need_prot = PROT_READ | PROT_WRITE;
#if !defined(CONFIG_TCG_INTERPRETER) && !defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifndef CONFIG_TCG_INTERPRETER
if (tcg_splitwx_diff == 0) {
need_prot |= host_prot_read_exec();
}
tcg/tcg.c
+6 -11
View File
@@ -246,7 +246,7 @@ TCGv_env tcg_env;
const void *tcg_code_gen_epilogue;
uintptr_t tcg_splitwx_diff;
#if !defined(CONFIG_TCG_INTERPRETER) && !defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifndef CONFIG_TCG_INTERPRETER
tcg_prologue_fn *tcg_qemu_tb_exec;
#endif
@@ -1413,7 +1413,7 @@ void tcg_prologue_init(void)
s->code_buf = s->code_gen_ptr;
s->data_gen_ptr = NULL;
#if !defined(CONFIG_TCG_INTERPRETER) && !defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifndef CONFIG_TCG_INTERPRETER
tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr);
#endif
@@ -1436,7 +1436,7 @@ void tcg_prologue_init(void)
prologue_size = tcg_current_code_size(s);
perf_report_prologue(s->code_gen_ptr, prologue_size);
#if !defined(CONFIG_TCG_INTERPRETER) && !defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifndef CONFIG_TCG_INTERPRETER
flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf),
(uintptr_t)s->code_buf, prologue_size);
#endif
@@ -1473,7 +1473,7 @@ void tcg_prologue_init(void)
}
}
#if !defined(CONFIG_TCG_INTERPRETER) && !defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifndef CONFIG_TCG_INTERPRETER
/*
* Assert that goto_ptr is implemented completely, setting an epilogue.
* For tci, we use NULL as the signal to return from the interpreter,
@@ -1941,12 +1941,6 @@ bool tcg_op_supported(TCGOpcode op)
= TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256;
switch (op) {
case INDEX_op_goto_ptr:
#if defined(CONFIG_TCG_THREADED_INTERPRETER)
return false;
#else
return true;
#endif
case INDEX_op_discard:
case INDEX_op_set_label:
case INDEX_op_call:
@@ -1955,6 +1949,7 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_insn_start:
case INDEX_op_exit_tb:
case INDEX_op_goto_tb:
case INDEX_op_goto_ptr:
case INDEX_op_qemu_ld_a32_i32:
case INDEX_op_qemu_ld_a64_i32:
case INDEX_op_qemu_st_a32_i32:
@@ -6280,7 +6275,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
return -2;
}
#if !defined(CONFIG_TCG_INTERPRETER) && !defined(CONFIG_TCG_THREADED_INTERPRETER)
#ifndef CONFIG_TCG_INTERPRETER
/* flush instruction cache */
flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf),
(uintptr_t)s->code_buf,