Compare commits
11 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 clobber
|
3ebf7e57eb | ||
|
clobber
|
576e14d64c | ||
 C.W. Betts
|
95b9099b3e | ||
|
C.W. Betts
|
90c519eb1e | ||
|
C.W. Betts
|
779baa7fca | ||
|
C.W. Betts
|
4f13fea4e2 | ||
|
clobber
|
17f423cfbd | ||
|
clobber
|
975a3e3266 | ||
|
clobber
|
17788c3ddd | ||
|
clobber
|
15af996d79 | ||
|
C.W. Betts
|
2c0279c0ac |
Binary file not shown.
@@ -47,6 +47,8 @@
|
||||
static const double pal_fps = 53203424.0 / (3420.0 * 313.0);
|
||||
static const double ntsc_fps = 53693175.0 / (3420.0 * 262.0);
|
||||
|
||||
t_config config;
|
||||
|
||||
char GG_ROM[256];
|
||||
char AR_ROM[256];
|
||||
char SK_ROM[256];
|
||||
|
||||
@@ -126,10 +126,10 @@
|
||||
/* End PBXCopyFilesBuildPhase section */
|
||||
|
||||
/* Begin PBXFileReference section */
|
||||
089C1672FE841209C02AAC07 /* Foundation.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = Foundation.framework; path = /System/Library/Frameworks/Foundation.framework; sourceTree = "<absolute>"; };
|
||||
089C167EFE841241C02AAC07 /* English */ = {isa = PBXFileReference; fileEncoding = 10; lastKnownFileType = text.plist.strings; name = English; path = English.lproj/InfoPlist.strings; sourceTree = "<group>"; };
|
||||
089C167FFE841241C02AAC07 /* AppKit.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = AppKit.framework; path = /System/Library/Frameworks/AppKit.framework; sourceTree = "<absolute>"; };
|
||||
1058C7ADFEA557BF11CA2CBB /* Cocoa.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = Cocoa.framework; path = /System/Library/Frameworks/Cocoa.framework; sourceTree = "<absolute>"; };
|
||||
089C1672FE841209C02AAC07 /* Foundation.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = Foundation.framework; path = System/Library/Frameworks/Foundation.framework; sourceTree = SDKROOT; };
|
||||
089C167EFE841241C02AAC07 /* en */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.strings; name = en; path = en.lproj/InfoPlist.strings; sourceTree = "<group>"; };
|
||||
089C167FFE841241C02AAC07 /* AppKit.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = AppKit.framework; path = System/Library/Frameworks/AppKit.framework; sourceTree = SDKROOT; };
|
||||
1058C7ADFEA557BF11CA2CBB /* Cocoa.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = Cocoa.framework; path = System/Library/Frameworks/Cocoa.framework; sourceTree = SDKROOT; };
|
||||
82287C08101E9C2C0072172D /* libz.dylib */ = {isa = PBXFileReference; lastKnownFileType = "compiled.mach-o.dylib"; name = libz.dylib; path = usr/lib/libz.dylib; sourceTree = SDKROOT; };
|
||||
82287C33101E9DB40072172D /* GenPlusGameCore.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = GenPlusGameCore.h; sourceTree = "<group>"; };
|
||||
82287C34101E9DB40072172D /* GenPlusGameCore.m */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.objc; path = GenPlusGameCore.m; sourceTree = "<group>"; };
|
||||
@@ -138,9 +138,9 @@
|
||||
879243AD1C0D044B0064C515 /* xe_1ap.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = xe_1ap.h; sourceTree = "<group>"; };
|
||||
879243AF1C0D05120064C515 /* graphic_board.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = graphic_board.c; sourceTree = "<group>"; };
|
||||
879243B01C0D05120064C515 /* graphic_board.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = graphic_board.h; sourceTree = "<group>"; };
|
||||
87D7BFC01F9841EE000B38DE /* OESMSSystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OESMSSystemResponderClient.h; path = ../OpenEmu/SegaMasterSystem/OESMSSystemResponderClient.h; sourceTree = "<group>"; };
|
||||
87D7BFC11F9841F8000B38DE /* OEGGSystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OEGGSystemResponderClient.h; path = ../OpenEmu/GameGear/OEGGSystemResponderClient.h; sourceTree = "<group>"; };
|
||||
87D7BFC21F984206000B38DE /* OESG1000SystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OESG1000SystemResponderClient.h; path = "../OpenEmu/SG-1000/OESG1000SystemResponderClient.h"; sourceTree = "<group>"; };
|
||||
87D7BFC01F9841EE000B38DE /* OESMSSystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OESMSSystemResponderClient.h; path = ../OpenEmu/SystemPlugins/SegaMasterSystem/OESMSSystemResponderClient.h; sourceTree = "<group>"; };
|
||||
87D7BFC11F9841F8000B38DE /* OEGGSystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OEGGSystemResponderClient.h; path = ../OpenEmu/SystemPlugins/GameGear/OEGGSystemResponderClient.h; sourceTree = "<group>"; };
|
||||
87D7BFC21F984206000B38DE /* OESG1000SystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OESG1000SystemResponderClient.h; path = "../OpenEmu/SystemPlugins/SG-1000/OESG1000SystemResponderClient.h"; sourceTree = "<group>"; };
|
||||
87E0514A1B18092700E870E1 /* osd.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = osd.h; sourceTree = "<group>"; };
|
||||
87E0514B1B18092700E870E1 /* scrc32.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = scrc32.c; sourceTree = "<group>"; };
|
||||
87E0514C1B18092700E870E1 /* scrc32.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = scrc32.h; sourceTree = "<group>"; };
|
||||
@@ -156,7 +156,7 @@
|
||||
941FF4F8162A4BAE005A9427 /* eeprom_spi.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = eeprom_spi.h; sourceTree = "<group>"; };
|
||||
941FF4FC162A4BE1005A9427 /* blip_buf.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = blip_buf.c; sourceTree = "<group>"; };
|
||||
941FF4FD162A4BE1005A9427 /* blip_buf.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = blip_buf.h; sourceTree = "<group>"; };
|
||||
946C18AE17148D5200C64BF9 /* OESegaCDSystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OESegaCDSystemResponderClient.h; path = "../OpenEmu/Sega CD/OESegaCDSystemResponderClient.h"; sourceTree = "<group>"; };
|
||||
946C18AE17148D5200C64BF9 /* OESegaCDSystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OESegaCDSystemResponderClient.h; path = "../OpenEmu/SystemPlugins/Sega CD/OESegaCDSystemResponderClient.h"; sourceTree = "<group>"; };
|
||||
948DA2A115AB906400C0EA78 /* cd_cart.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = cd_cart.c; sourceTree = "<group>"; };
|
||||
948DA2A215AB906400C0EA78 /* cd_cart.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = cd_cart.h; sourceTree = "<group>"; };
|
||||
948DA2A315AB906400C0EA78 /* cdc.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = cdc.c; sourceTree = "<group>"; };
|
||||
@@ -256,9 +256,9 @@
|
||||
94ED8A8514CF933700FF8901 /* osd_cpu.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = osd_cpu.h; sourceTree = "<group>"; };
|
||||
94ED8A8614CF933700FF8901 /* z80.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = z80.c; sourceTree = "<group>"; };
|
||||
94ED8A8714CF933700FF8901 /* z80.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = z80.h; sourceTree = "<group>"; };
|
||||
C6B948191365164700A425F0 /* OEGenesisSystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OEGenesisSystemResponderClient.h; path = ../OpenEmu/Genesis/OEGenesisSystemResponderClient.h; sourceTree = "<group>"; };
|
||||
C6B948191365164700A425F0 /* OEGenesisSystemResponderClient.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = OEGenesisSystemResponderClient.h; path = ../OpenEmu/SystemPlugins/Genesis/OEGenesisSystemResponderClient.h; sourceTree = "<group>"; };
|
||||
C6D120F1171130E700E868A8 /* OpenEmuBase.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; path = OpenEmuBase.framework; sourceTree = BUILT_PRODUCTS_DIR; };
|
||||
D2F7E65807B2D6F200F64583 /* CoreData.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = CoreData.framework; path = /System/Library/Frameworks/CoreData.framework; sourceTree = "<absolute>"; };
|
||||
D2F7E65807B2D6F200F64583 /* CoreData.framework */ = {isa = PBXFileReference; lastKnownFileType = wrapper.framework; name = CoreData.framework; path = System/Library/Frameworks/CoreData.framework; sourceTree = SDKROOT; };
|
||||
/* End PBXFileReference section */
|
||||
|
||||
/* Begin PBXFrameworksBuildPhase section */
|
||||
@@ -570,15 +570,13 @@
|
||||
089C1669FE841209C02AAC07 /* Project object */ = {
|
||||
isa = PBXProject;
|
||||
attributes = {
|
||||
BuildIndependentTargetsInParallel = YES;
|
||||
LastUpgradeCheck = 0700;
|
||||
};
|
||||
buildConfigurationList = 1DEB913E08733D840010E9CD /* Build configuration list for PBXProject "GenesisPlus" */;
|
||||
compatibilityVersion = "Xcode 3.2";
|
||||
developmentRegion = English;
|
||||
developmentRegion = en;
|
||||
hasScannedForEncodings = 1;
|
||||
knownRegions = (
|
||||
English,
|
||||
en,
|
||||
);
|
||||
mainGroup = 089C166AFE841209C02AAC07 /* GenesisPlus */;
|
||||
@@ -715,7 +713,7 @@
|
||||
089C167DFE841241C02AAC07 /* InfoPlist.strings */ = {
|
||||
isa = PBXVariantGroup;
|
||||
children = (
|
||||
089C167EFE841241C02AAC07 /* English */,
|
||||
089C167EFE841241C02AAC07 /* en */,
|
||||
);
|
||||
name = InfoPlist.strings;
|
||||
sourceTree = "<group>";
|
||||
@@ -735,6 +733,7 @@
|
||||
OTHER_CFLAGS = (
|
||||
"-DLSB_FIRST",
|
||||
"-DUSE_32BPP_RENDERING",
|
||||
"-DMAXROMSIZE=33554432",
|
||||
);
|
||||
PRODUCT_BUNDLE_IDENTIFIER = "org.openemu.${PRODUCT_NAME:identifier}";
|
||||
PRODUCT_NAME = GenesisPlus;
|
||||
@@ -755,6 +754,7 @@
|
||||
OTHER_CFLAGS = (
|
||||
"-DLSB_FIRST",
|
||||
"-DUSE_32BPP_RENDERING",
|
||||
"-DMAXROMSIZE=33554432",
|
||||
);
|
||||
PRODUCT_BUNDLE_IDENTIFIER = "org.openemu.${PRODUCT_NAME:identifier}";
|
||||
PRODUCT_NAME = GenesisPlus;
|
||||
|
||||
+3
-3
@@ -3,7 +3,7 @@
|
||||
<plist version="1.0">
|
||||
<dict>
|
||||
<key>CFBundleDevelopmentRegion</key>
|
||||
<string>English</string>
|
||||
<string>$(DEVELOPMENT_LANGUAGE)</string>
|
||||
<key>CFBundleExecutable</key>
|
||||
<string>${EXECUTABLE_NAME}</string>
|
||||
<key>CFBundleIconFile</key>
|
||||
@@ -19,7 +19,7 @@
|
||||
<key>CFBundleSignature</key>
|
||||
<string>????</string>
|
||||
<key>CFBundleVersion</key>
|
||||
<string>1.7.4.11</string>
|
||||
<string>1.7.4.14</string>
|
||||
<key>NSPrincipalClass</key>
|
||||
<string>OEGameCoreController</string>
|
||||
<key>OEGameCoreClass</key>
|
||||
@@ -122,7 +122,7 @@
|
||||
<key>OEGameCorePlayerCount</key>
|
||||
<string>8</string>
|
||||
<key>OEProjectURL</key>
|
||||
<string>http://code.google.com/p/genplus-gx</string>
|
||||
<string>https://github.com/ekeeke/Genesis-Plus-GX</string>
|
||||
<key>OESystemIdentifiers</key>
|
||||
<array>
|
||||
<string>openemu.system.sg1000</string>
|
||||
|
||||
@@ -0,0 +1,2 @@
|
||||
/* Localized versions of Info.plist keys */
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/****************************************************************************
|
||||
* Genesis Plus
|
||||
* Action Replay / Pro Action Replay emulation
|
||||
* Action Replay / Pro Action Replay hardware support
|
||||
*
|
||||
* Copyright (C) 2009-2014 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2009-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -45,8 +45,7 @@ static struct
|
||||
{
|
||||
uint8 enabled;
|
||||
uint8 status;
|
||||
uint8 *rom;
|
||||
uint8 *ram;
|
||||
uint8 ram[0x10000];
|
||||
uint16 regs[13];
|
||||
uint16 old[4];
|
||||
uint16 data[4];
|
||||
@@ -54,64 +53,52 @@ static struct
|
||||
} action_replay;
|
||||
|
||||
static void ar_write_regs(uint32 address, uint32 data);
|
||||
static void ar_write_regs_2(uint32 address, uint32 data);
|
||||
static void ar2_write_reg(uint32 address, uint32 data);
|
||||
static void ar_write_ram_8(uint32 address, uint32 data);
|
||||
|
||||
void areplay_init(void)
|
||||
{
|
||||
int size;
|
||||
|
||||
memset(&action_replay,0,sizeof(action_replay));
|
||||
action_replay.enabled = action_replay.status = 0;
|
||||
|
||||
/* store Action replay ROM (max. 128k) & RAM (64k) above cartridge ROM + SRAM area */
|
||||
if (cart.romsize > 0x810000) return;
|
||||
action_replay.rom = cart.rom + 0x810000;
|
||||
action_replay.ram = cart.rom + 0x830000;
|
||||
|
||||
/* try to load Action Replay ROM file */
|
||||
size = load_archive(AR_ROM, action_replay.rom, 0x20000, NULL);
|
||||
|
||||
/* detect Action Replay board type */
|
||||
switch (size)
|
||||
/* try to load Action Replay ROM file (max. 64KB) */
|
||||
if (load_archive(AR_ROM, cart.lockrom, 0x10000, NULL) > 0)
|
||||
{
|
||||
case 0x8000:
|
||||
/* detect Action Replay board type */
|
||||
if (!memcmp(cart.lockrom + 0x120, "ACTION REPLAY ", 16))
|
||||
{
|
||||
if (!memcmp(action_replay.rom + 0x120, "ACTION REPLAY ", 16))
|
||||
{
|
||||
/* normal Action Replay (32K) */
|
||||
action_replay.enabled = TYPE_AR;
|
||||
|
||||
/* internal registers mapped at $010000-$01ffff */
|
||||
m68k.memory_map[0x01].write16 = ar_write_regs;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* normal Action Replay (32KB ROM) */
|
||||
action_replay.enabled = TYPE_AR;
|
||||
|
||||
case 0x10000:
|
||||
case 0x20000:
|
||||
/* $0000-$7fff mirrored into $8000-$ffff */
|
||||
memcpy(cart.lockrom + 0x8000, cart.lockrom, 0x8000);
|
||||
|
||||
/* internal registers mapped at $010000-$01ffff */
|
||||
m68k.memory_map[0x01].write16 = ar_write_regs;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Read stack pointer MSB */
|
||||
uint8 sp = READ_BYTE(action_replay.rom, 0x01);
|
||||
uint8 sp = cart.lockrom[0x01];
|
||||
|
||||
/* Detect board version */
|
||||
if ((sp == 0x42) && !memcmp(action_replay.rom + 0x120, "ACTION REPLAY 2 ", 16))
|
||||
if ((sp == 0x42) && !memcmp(cart.lockrom + 0x120, "ACTION REPLAY 2 ", 16))
|
||||
{
|
||||
/* PRO Action Replay 1 (64/128K) */
|
||||
/* PRO Action Replay (2x32KB ROM) */
|
||||
action_replay.enabled = TYPE_PRO1;
|
||||
|
||||
/* internal registers mapped at $010000-$01ffff */
|
||||
m68k.memory_map[0x01].write16 = ar_write_regs;
|
||||
}
|
||||
else if ((sp == 0x60) && !memcmp(action_replay.rom + 0x3c6, "ACTION REPLAY II", 16))
|
||||
else if ((sp == 0x60) && !memcmp(cart.lockrom + 0x3c6, "ACTION REPLAY II", 16))
|
||||
{
|
||||
/* PRO Action Replay 2 (64K) */
|
||||
/* PRO Action Replay 2 (2x32KB ROM) */
|
||||
action_replay.enabled = TYPE_PRO2;
|
||||
|
||||
/* internal registers mapped at $100000-$10ffff */
|
||||
m68k.memory_map[0x10].write16 = ar_write_regs_2;
|
||||
/* internal register mapped at $100000-$10ffff */
|
||||
m68k.memory_map[0x10].write16 = ar2_write_reg;
|
||||
}
|
||||
|
||||
/* internal RAM (64k), mapped at $420000-$42ffff or $600000-$60ffff */
|
||||
/* internal RAM (64KB), mapped at $420000-$42ffff or $600000-$60ffff */
|
||||
if (action_replay.enabled)
|
||||
{
|
||||
m68k.memory_map[sp].base = action_replay.ram;
|
||||
@@ -120,28 +107,22 @@ void areplay_init(void)
|
||||
m68k.memory_map[sp].write8 = ar_write_ram_8;
|
||||
m68k.memory_map[sp].write16 = NULL;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef LSB_FIRST
|
||||
if (action_replay.enabled)
|
||||
{
|
||||
int i;
|
||||
for (i= 0; i<size; i+=2)
|
||||
if (action_replay.enabled)
|
||||
{
|
||||
/* Byteswap ROM */
|
||||
uint8 temp = action_replay.rom[i];
|
||||
action_replay.rom[i] = action_replay.rom[i+1];
|
||||
action_replay.rom[i+1] = temp;
|
||||
int i;
|
||||
for (i= 0; i<0x10000; i+=2)
|
||||
{
|
||||
/* Byteswap ROM */
|
||||
uint8 temp = cart.lockrom[i];
|
||||
cart.lockrom[i] = cart.lockrom[i+1];
|
||||
cart.lockrom[i+1] = temp;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void areplay_shutdown(void)
|
||||
@@ -166,7 +147,7 @@ void areplay_reset(int hard)
|
||||
memset(action_replay.addr, 0, sizeof(action_replay.addr));
|
||||
|
||||
/* by default, internal ROM is mapped at $000000-$00FFFF */
|
||||
m68k.memory_map[0].base = action_replay.rom;
|
||||
m68k.memory_map[0].base = cart.lockrom;
|
||||
|
||||
/* reset internal RAM on power-on */
|
||||
if (hard)
|
||||
@@ -287,7 +268,7 @@ static void ar_write_regs(uint32 address, uint32 data)
|
||||
}
|
||||
}
|
||||
|
||||
static void ar_write_regs_2(uint32 address, uint32 data)
|
||||
static void ar2_write_reg(uint32 address, uint32 data)
|
||||
{
|
||||
/* enable Cartridge ROM */
|
||||
if (((address & 0xff) == 0x78) && (data == 0xffff))
|
||||
@@ -301,4 +282,3 @@ static void ar_write_ram_8(uint32 address, uint32 data)
|
||||
/* byte writes are handled as word writes, with LSB duplicated in MSB (/LWR is not used) */
|
||||
*(uint16 *)(action_replay.ram + (address & 0xfffe)) = (data | (data << 8));
|
||||
}
|
||||
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/****************************************************************************
|
||||
* Genesis Plus
|
||||
* DATEL Action Replay / Pro Action Replay emulation
|
||||
* Action Replay / Pro Action Replay hardware support
|
||||
*
|
||||
* Copyright (C) 2009-2014 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2009-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/****************************************************************************
|
||||
* Genesis Plus
|
||||
* Game Genie Hardware emulation
|
||||
* Game Genie hardware support
|
||||
*
|
||||
* Copyright (C) 2009-2014 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2009-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Based on documentation from Charles McDonald
|
||||
* (http://cgfm2.emuviews.com/txt/genie.txt)
|
||||
@@ -44,7 +44,6 @@
|
||||
static struct
|
||||
{
|
||||
uint8 enabled;
|
||||
uint8 *rom;
|
||||
uint16 regs[0x20];
|
||||
uint16 old[6];
|
||||
uint16 data[6];
|
||||
@@ -58,29 +57,25 @@ static void ggenie_write_word(unsigned int address, unsigned int data);
|
||||
static void ggenie_write_regs(unsigned int offset, unsigned int data);
|
||||
|
||||
void ggenie_init(void)
|
||||
{
|
||||
memset(&ggenie,0,sizeof(ggenie));
|
||||
{
|
||||
ggenie.enabled = 0;
|
||||
|
||||
/* Store Game Genie ROM (32k) above cartridge ROM + SRAM area */
|
||||
if (cart.romsize > 0x810000) return;
|
||||
ggenie.rom = cart.rom + 0x810000;
|
||||
|
||||
/* Try to load Game Genie ROM file */
|
||||
if (load_archive(GG_ROM, ggenie.rom, 0x8000, NULL) > 0)
|
||||
/* Try to load Game Genie ROM file (32KB) */
|
||||
if (load_archive(GG_ROM, cart.lockrom, 0x8000, NULL) > 0)
|
||||
{
|
||||
#ifdef LSB_FIRST
|
||||
int i;
|
||||
for (i=0; i<0x8000; i+=2)
|
||||
{
|
||||
/* Byteswap ROM */
|
||||
uint8 temp = ggenie.rom[i];
|
||||
ggenie.rom[i] = ggenie.rom[i+1];
|
||||
ggenie.rom[i+1] = temp;
|
||||
uint8 temp = cart.lockrom[i];
|
||||
cart.lockrom[i] = cart.lockrom[i+1];
|
||||
cart.lockrom[i+1] = temp;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* $0000-$7fff mirrored into $8000-$ffff */
|
||||
memcpy(ggenie.rom + 0x8000, ggenie.rom, 0x8000);
|
||||
memcpy(cart.lockrom + 0x8000, cart.lockrom, 0x8000);
|
||||
|
||||
/* Game Genie hardware is enabled */
|
||||
ggenie.enabled = 1;
|
||||
@@ -113,7 +108,7 @@ void ggenie_reset(int hard)
|
||||
}
|
||||
|
||||
/* Game Genie ROM is mapped at $000000-$007fff */
|
||||
m68k.memory_map[0].base = ggenie.rom;
|
||||
m68k.memory_map[0].base = cart.lockrom;
|
||||
|
||||
/* Internal registers are mapped at $000000-$00001f */
|
||||
m68k.memory_map[0].write8 = ggenie_write_byte;
|
||||
@@ -214,7 +209,7 @@ static void ggenie_write_regs(unsigned int offset, unsigned int data)
|
||||
else
|
||||
{
|
||||
/* $0000-$7ffff reads mapped to Game Genie ROM */
|
||||
m68k.memory_map[0].base = ggenie.rom;
|
||||
m68k.memory_map[0].base = cart.lockrom;
|
||||
m68k.memory_map[0].read8 = NULL;
|
||||
m68k.memory_map[0].read16 = NULL;
|
||||
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/****************************************************************************
|
||||
* Genesis Plus
|
||||
* Game Genie Hardware emulation
|
||||
* Game Genie hardware support
|
||||
*
|
||||
* Copyright (C) 2009-2014 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2009-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Based on documentation from Charles McDonald
|
||||
* (http://cgfm2.emuviews.com/txt/genie.txt)
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* Mega Drive cartridge hardware support
|
||||
*
|
||||
* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Many cartridge protections were initially documented by Haze
|
||||
* (http://haze.mameworld.info/)
|
||||
@@ -74,7 +74,12 @@ static void mapper_seganet_w(uint32 address, uint32 data);
|
||||
static void mapper_32k_w(uint32 data);
|
||||
static void mapper_64k_w(uint32 data);
|
||||
static void mapper_64k_multi_w(uint32 address);
|
||||
static uint32 mapper_radica_r(uint32 address);
|
||||
static uint32 mapper_128k_multi_r(uint32 address);
|
||||
static void mapper_256k_multi_w(uint32 address, uint32 data);
|
||||
static void mapper_wd1601_w(uint32 address, uint32 data);
|
||||
static uint32 mapper_64k_radica_r(uint32 address);
|
||||
static uint32 mapper_128k_radica_r(uint32 address);
|
||||
static void mapper_sr16v1_w(uint32 address, uint32 data);
|
||||
static void default_time_w(uint32 address, uint32 data);
|
||||
static void default_regs_w(uint32 address, uint32 data);
|
||||
static uint32 default_regs_r(uint32 address);
|
||||
@@ -102,13 +107,26 @@ static const md_entry_t rom_database[] =
|
||||
/* Tom Clown */
|
||||
{0x0000,0xc0cd,0x40,0x40,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},1,0,NULL,NULL,NULL,mapper_realtec_w}},
|
||||
|
||||
/* 1800-in-1 */
|
||||
{0x3296,0x2370,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,1,mapper_128k_multi_r,m68k_unused_8_w,NULL,NULL}},
|
||||
|
||||
/* Golden Mega 250-in-1 */
|
||||
{0xe43c,0x886f,0x08,0x08,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,1,NULL,m68k_unused_8_w,NULL,mapper_256k_multi_w}},
|
||||
|
||||
/* RADICA (Volume 1) (bad dump ?) */
|
||||
{0x0000,0x2326,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,1,mapper_radica_r,NULL,NULL,NULL}},
|
||||
{0x0000,0x2326,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,1,mapper_64k_radica_r,m68k_unused_8_w,NULL,NULL}},
|
||||
/* RADICA (Volume 1) */
|
||||
{0x24f4,0xfc84,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,0,mapper_radica_r,NULL,NULL,NULL}},
|
||||
{0x24f4,0xfc84,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,0,mapper_64k_radica_r,m68k_unused_8_w,NULL,NULL}},
|
||||
/* RADICA (Volume 2) */
|
||||
{0x104f,0x32e9,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,0,mapper_radica_r,NULL,NULL,NULL}},
|
||||
{0xd951,0x78d0,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,0,mapper_64k_radica_r,m68k_unused_8_w,NULL,NULL}},
|
||||
/* RADICA (Volume 3 - Super Sonic Gold edition) */
|
||||
{0x0000,0x1f25,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,0,mapper_64k_radica_r,m68k_unused_8_w,NULL,NULL}},
|
||||
/* RADICA (Street Fighter II CE edition) */
|
||||
{0x1add,0xa838,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,0,mapper_64k_radica_r,m68k_unused_8_w,NULL,NULL}},
|
||||
/* RADICA (Street Fighter II CE edition) (PAL) */
|
||||
{0x104f,0x32e9,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,0,mapper_64k_radica_r,m68k_unused_8_w,NULL,NULL}},
|
||||
/* RADICA (Sensible Soccer Plus edition) (PAL) */
|
||||
{0x0000,0x1f7f,0x00,0x00,{{0x00,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x000000,0x000000,0x000000,0x000000},0,0,mapper_128k_radica_r,m68k_unused_8_w,NULL,NULL}},
|
||||
|
||||
|
||||
/* Tenchi wo Kurau III: Sangokushi Gaiden - Chinese Fighter */
|
||||
@@ -210,6 +228,12 @@ static const md_entry_t rom_database[] =
|
||||
{0x0000,0xd0a0,0x48,0x4f,{{0x00,0x00,0xaa,0xf0},{0xffffff,0xffffff,0xfc0000,0xfc0000},{0x000000,0x000000,0x480000,0x4c0000},0,0,NULL,NULL,default_regs_r,NULL}},
|
||||
|
||||
|
||||
/* Rock Heaven */
|
||||
{0x6cca,0x2395,0x50,0x50,{{0x50,0x00,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x500008,0x000000,0x000000,0x000000},0,0,NULL,NULL,default_regs_r,NULL}},
|
||||
/* Rock World */
|
||||
{0x3547,0xa3da,0x50,0x50,{{0x50,0xa0,0x00,0x00},{0xffffff,0xffffff,0xffffff,0xffffff},{0x500008,0x500208,0x000000,0x000000},0,0,NULL,NULL,default_regs_r,NULL}},
|
||||
|
||||
|
||||
/* Rockman X3 (bootleg version ? two last register returned values are ignored, note that 0xaa/0x18 would work as well) */
|
||||
{0x0000,0x9d0e,0x40,0x40,{{0x0c,0x00,0xc9,0xf0},{0xffffff,0xffffff,0xffffff,0xffffff},{0xa13000,0x000000,0x400004,0x400006},0,0,default_regs_r,NULL,default_regs_r,NULL}},
|
||||
|
||||
@@ -391,11 +415,12 @@ void md_cart_init(void)
|
||||
zbank_memory_map[sram.start >> 16].write = sram_write_byte;
|
||||
}
|
||||
|
||||
/* support for Triple Play 96 & Triple Play - Gold Edition (available ROM dumps include dumped SRAM data) */
|
||||
/* support for Triple Play 96 & Triple Play - Gold Edition mapping */
|
||||
else if ((strstr(rominfo.product,"T-172026") != NULL) || (strstr(rominfo.product,"T-172116") != NULL))
|
||||
{
|
||||
/* $000000-$1fffff and $300000-$3fffff: cartridge ROM (2MB + 1MB) */
|
||||
/* $200000-$2fffff: SRAM (32 KB mirrored) */
|
||||
/* $000000-$1fffff: cartridge ROM (lower 2MB) */
|
||||
/* $200000-$2fffff: SRAM (32KB mirrored) */
|
||||
/* NB: existing 4MB ROM dumps include SRAM data at ROM offsets 0x200000-0x2fffff */
|
||||
for (i=0x20; i<0x30; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = sram.sram;
|
||||
@@ -406,6 +431,16 @@ void md_cart_init(void)
|
||||
zbank_memory_map[i].read = sram_read_byte;
|
||||
zbank_memory_map[i].write = sram_write_byte;
|
||||
}
|
||||
|
||||
/* $300000-$3fffff: cartridge ROM (upper 1MB) */
|
||||
/* NB: only real (3MB) Mask ROM dumps need ROM offsets 0x200000-0x2fffff to be remapped to this area */
|
||||
if (READ_BYTE(cart.rom, 0x200000) != 0xFF)
|
||||
{
|
||||
for (i=0x30; i<0x40; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = cart.rom + ((i - 0x10) << 16);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -413,84 +448,11 @@ void md_cart_init(void)
|
||||
SVP CHIP
|
||||
***********************************************/
|
||||
svp = NULL;
|
||||
if (strstr(rominfo.international,"Virtua Racing"))
|
||||
if ((READ_BYTE(cart.rom, 0x1c8) == 'S') && (READ_BYTE(cart.rom, 0x1c9) == 'V'))
|
||||
{
|
||||
svp_init();
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
LOCK-ON
|
||||
***********************************************/
|
||||
|
||||
/* clear existing patches */
|
||||
ggenie_shutdown();
|
||||
areplay_shutdown();
|
||||
|
||||
/* initialize extra hardware */
|
||||
switch (config.lock_on)
|
||||
{
|
||||
case TYPE_GG:
|
||||
{
|
||||
ggenie_init();
|
||||
break;
|
||||
}
|
||||
|
||||
case TYPE_AR:
|
||||
{
|
||||
areplay_init();
|
||||
break;
|
||||
}
|
||||
|
||||
case TYPE_SK:
|
||||
{
|
||||
/* store S&K ROM above cartridge ROM (and before backup memory) */
|
||||
if (cart.romsize > 0x600000) break;
|
||||
|
||||
/* try to load Sonic & Knuckles ROM file (2 MB) */
|
||||
if (load_archive(SK_ROM, cart.rom + 0x600000, 0x200000, NULL) == 0x200000)
|
||||
{
|
||||
/* check ROM header */
|
||||
if (!memcmp(cart.rom + 0x600000 + 0x120, "SONIC & KNUCKLES",16))
|
||||
{
|
||||
/* try to load Sonic 2 & Knuckles UPMEM ROM (256 KB) */
|
||||
if (load_archive(SK_UPMEM, cart.rom + 0x900000, 0x40000, NULL) == 0x40000)
|
||||
{
|
||||
/* $000000-$1FFFFF is mapped to S&K ROM */
|
||||
for (i=0x00; i<0x20; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = cart.rom + 0x600000 + (i << 16);
|
||||
}
|
||||
|
||||
#ifdef LSB_FIRST
|
||||
for (i=0; i<0x200000; i+=2)
|
||||
{
|
||||
/* Byteswap ROM */
|
||||
uint8 temp = cart.rom[i + 0x600000];
|
||||
cart.rom[i + 0x600000] = cart.rom[i + 0x600000 + 1];
|
||||
cart.rom[i + 0x600000 + 1] = temp;
|
||||
}
|
||||
|
||||
for (i=0; i<0x40000; i+=2)
|
||||
{
|
||||
/* Byteswap ROM */
|
||||
uint8 temp = cart.rom[i + 0x900000];
|
||||
cart.rom[i + 0x900000] = cart.rom[i + 0x900000 + 1];
|
||||
cart.rom[i + 0x900000 + 1] = temp;
|
||||
}
|
||||
#endif
|
||||
cart.special |= HW_LOCK_ON;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
CARTRIDGE EXTRA HARDWARE
|
||||
***********************************************/
|
||||
@@ -534,16 +496,16 @@ void md_cart_init(void)
|
||||
/* Realtec mapper */
|
||||
if (cart.hw.realtec)
|
||||
{
|
||||
/* 8k BOOT ROM */
|
||||
/* copy 8KB Boot ROM after cartridge ROM area */
|
||||
for (i=0; i<8; i++)
|
||||
{
|
||||
memcpy(cart.rom + 0x900000 + i*0x2000, cart.rom + 0x7e000, 0x2000);
|
||||
memcpy(cart.rom + 0x400000 + i*0x2000, cart.rom + 0x7e000, 0x2000);
|
||||
}
|
||||
|
||||
/* BOOT ROM is mapped to $000000-$3FFFFF */
|
||||
/* Boot ROM (8KB mirrored) is mapped to $000000-$3FFFFF */
|
||||
for (i=0x00; i<0x40; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = cart.rom + 0x900000;
|
||||
m68k.memory_map[i].base = cart.rom + 0x400000;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -657,6 +619,20 @@ void md_cart_init(void)
|
||||
m68k.memory_map[0x00].write16 = mapper_flashkit_w;
|
||||
zbank_memory_map[0x00].write = mapper_flashkit_w;
|
||||
}
|
||||
else if ((cart.romsize == 0x400000) &&
|
||||
(READ_BYTE(cart.rom, 0x200150) == 'C') &&
|
||||
(READ_BYTE(cart.rom, 0x200151) == 'A') &&
|
||||
(READ_BYTE(cart.rom, 0x200152) == 'N') &&
|
||||
(READ_BYTE(cart.rom, 0x200153) == 'O') &&
|
||||
(READ_BYTE(cart.rom, 0x200154) == 'N'))
|
||||
{
|
||||
/* Canon - Legend of the new Gods (4MB dump) */
|
||||
cart.hw.time_w = mapper_wd1601_w;
|
||||
cart.hw.bankshift = 1;
|
||||
sram.on = 1;
|
||||
sram.start = 0x200000;
|
||||
sram.end = 0x201fff;
|
||||
}
|
||||
else if ((*(uint16 *)(cart.rom + 0x08) == 0x6000) && (*(uint16 *)(cart.rom + 0x0a) == 0x01f6) && (rominfo.realchecksum == 0xf894))
|
||||
{
|
||||
/* Super Mario World 64 (unlicensed) mapper */
|
||||
@@ -689,6 +665,11 @@ void md_cart_init(void)
|
||||
zbank_memory_map[i].write = mapper_smw_64_w;
|
||||
}
|
||||
}
|
||||
else if ((*(uint16 *)(cart.rom + 0x04) == 0x0000) && (*(uint16 *)(cart.rom + 0x06) == 0x0104) && (rominfo.checksum == 0x31fc))
|
||||
{
|
||||
/* Micro Machines (USA) custom TMSS bypass logic */
|
||||
m68k.memory_map[0xa1].write8 = mapper_sr16v1_w;
|
||||
}
|
||||
else if (cart.romsize > 0x400000)
|
||||
{
|
||||
/* assume linear ROM mapping by default (max. 10MB) */
|
||||
@@ -706,6 +687,79 @@ void md_cart_init(void)
|
||||
{
|
||||
cart.hw.time_w = default_time_w;
|
||||
}
|
||||
|
||||
/**********************************************
|
||||
LOCK-ON
|
||||
***********************************************/
|
||||
|
||||
/* clear existing patches */
|
||||
ggenie_shutdown();
|
||||
areplay_shutdown();
|
||||
|
||||
/* initialize extra hardware */
|
||||
switch (config.lock_on)
|
||||
{
|
||||
case TYPE_GG:
|
||||
{
|
||||
ggenie_init();
|
||||
break;
|
||||
}
|
||||
|
||||
case TYPE_AR:
|
||||
{
|
||||
areplay_init();
|
||||
break;
|
||||
}
|
||||
|
||||
case TYPE_SK:
|
||||
{
|
||||
/* store Sonic & Knuckles ROM files after cartridge ROM area */
|
||||
if (cart.romsize > 0x400000) break;
|
||||
|
||||
/* try to load Sonic & Knuckles ROM file (2MB) */
|
||||
if (load_archive(SK_ROM, cart.rom + 0x400000, 0x200000, NULL) == 0x200000)
|
||||
{
|
||||
/* check ROM header */
|
||||
if (!memcmp(cart.rom + 0x400000 + 0x120, "SONIC & KNUCKLES",16))
|
||||
{
|
||||
/* try to load Sonic 2 & Knuckles upmem ROM file (256KB) */
|
||||
if (load_archive(SK_UPMEM, cart.rom + 0x600000, 0x40000, NULL) == 0x40000)
|
||||
{
|
||||
/* $000000-$1FFFFF is mapped to S&K ROM */
|
||||
for (i=0x00; i<0x20; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = cart.rom + 0x400000 + (i << 16);
|
||||
}
|
||||
|
||||
#ifdef LSB_FIRST
|
||||
for (i=0; i<0x200000; i+=2)
|
||||
{
|
||||
/* Byteswap ROM */
|
||||
uint8 temp = cart.rom[i + 0x400000];
|
||||
cart.rom[i + 0x400000] = cart.rom[i + 0x400000 + 1];
|
||||
cart.rom[i + 0x400000 + 1] = temp;
|
||||
}
|
||||
|
||||
for (i=0; i<0x40000; i+=2)
|
||||
{
|
||||
/* Byteswap ROM */
|
||||
uint8 temp = cart.rom[i + 0x600000];
|
||||
cart.rom[i + 0x600000] = cart.rom[i + 0x600000 + 1];
|
||||
cart.rom[i + 0x600000 + 1] = temp;
|
||||
}
|
||||
#endif
|
||||
cart.special |= HW_LOCK_ON;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* hardware that need to be reseted on power on */
|
||||
@@ -899,12 +953,12 @@ static void mapper_sega_w(uint32 data)
|
||||
}
|
||||
|
||||
/* S&K lock-on chip */
|
||||
if ((cart.special & HW_LOCK_ON) && (config.lock_on == TYPE_SK))
|
||||
if (cart.special & HW_LOCK_ON)
|
||||
{
|
||||
/* S2K upmem chip mapped to $300000-$3fffff (256K mirrored) */
|
||||
/* S2K upmem chip mapped to $300000-$3fffff (256KB mirrored) */
|
||||
for (i=0x30; i<0x40; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = (cart.rom + 0x900000) + ((i & 3) << 16);
|
||||
m68k.memory_map[i].base = (cart.rom + 0x600000) + ((i & 3) << 16);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1646,27 +1700,231 @@ static void mapper_64k_multi_w(uint32 address)
|
||||
/* 64 x 64k banks */
|
||||
for (i=0; i<64; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = &cart.rom[((address++) & 0x3f) << 16];
|
||||
m68k.memory_map[i].base = &cart.rom[((address + i) & 0x3f) << 16];
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
Custom ROM Bankswitch used in pirate "1800-in-1" cartridge
|
||||
*/
|
||||
static uint32 mapper_128k_multi_r(uint32 address)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* 16 x 128k banks (2MB ROM) */
|
||||
/* Bank index (B3 B2 B1 B0) is encoded in address lower byte = {0 X B0 B1 X B2 B3 0} */
|
||||
/* Note: {0 B0 X B1 X B2 B3 0} also works, see below for the 9 unique values being used for all menu entries
|
||||
read16 00A13000 (0002FBEE) => 0x000000-0x03ffff (2x128KB)
|
||||
read16 00A13018 (00FF2056) => 0x040000-0x07ffff (2x128KB)
|
||||
read16 00A13004 (00FF2120) => 0x080000-0x0bffff (2x128KB)
|
||||
read16 00A1301C (00FF20A6) => 0x0c0000-0x0fffff (2x128KB)
|
||||
read16 00A1300A (00FF20BA) => 0x100000-0x13ffff (2x128KB)
|
||||
read16 00A1301A (00FF20CE) => 0x140000-0x17ffff (2x128KB)
|
||||
read16 00A1300E (00FF20F4) => 0x180000-0x1bffff (2x128KB)
|
||||
read16 00A1301E (00FF2136) => 0x1c0000-0x1dffff (1x128KB)
|
||||
read16 00A1307E (00FF2142) => 0x1e0000-0x1fffff (1x128KB)
|
||||
*/
|
||||
int bank = ((address & 0x02) << 2) | (address & 0x04) | ((address & 0x10) >> 3) | ((address & 0x20) >> 5);
|
||||
|
||||
/* remap cartridge area (64 x 64k banks) */
|
||||
address = bank << 1;
|
||||
for (i=0x00; i<0x40; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = &cart.rom[((address + i) & 0x3f) << 16];
|
||||
}
|
||||
|
||||
/* returned value changes the menu title and number of entries in the 'game' list (the number of distinct games does not change though) */
|
||||
/* 0x00 => 9-in-1 */
|
||||
/* 0x01 => 190-in-1 */
|
||||
/* 0x02 => 888-in-1 */
|
||||
/* 0x03 => 1800-in-1 */
|
||||
/* real cartridge board has switches to select between the four different menus but here we force the largest menu selection (each other menus being a subset of the next larger menu) */
|
||||
return 0x03;
|
||||
}
|
||||
|
||||
/*
|
||||
Custom ROM Bankswitch used in pirate "Golden Mega 250-in-1" cartridge
|
||||
*/
|
||||
static void mapper_256k_multi_w(uint32 address, uint32 data)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* 8 x 256k banks (2MB ROM) */
|
||||
/* Bank index (B2 B1 B0) is encoded in data lower byte = {B1 B0 X X 0 0 0 B2} */
|
||||
/* Note: {X B0 B1 B2 0 0 0 X}, {B1 B0 X B2 0 0 0 X} or {X B0 B1 X 0 0 0 B2} also work, see below for the 4 unique values being used for all menu entries
|
||||
write16 00089000 = 0000 (00FF0006) => 0x000000-0x03ffff (1x256KB)
|
||||
write16 00089000 = 0040 (00FF0006) => 0x040000-0x07ffff (1x256KB)
|
||||
write16 00089000 = 00A0 (00FF0006) => 0x080000-0x0fffff (2x256KB)
|
||||
write16 00089000 = 0011 (00FF0006) => 0x100000-0x1fffff (4x256KB)
|
||||
*/
|
||||
int bank = ((data & 0x01) << 2) | ((data & 0xc0) >> 6);
|
||||
|
||||
/* remap cartridge area (64 x 64k banks) */
|
||||
address = bank << 2;
|
||||
for (i=0x00; i<0x40; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = &cart.rom[((address + i) & 0x3f) << 16];
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
Custom ROM Bankswitch used in "Canon - Legend of the New Gods"
|
||||
(uses WD1601 QFPL V1.01 board also used in chinese X-in-1 pirates sold by mindkids)
|
||||
*/
|
||||
static void mapper_wd1601_w(uint32 address, uint32 data)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* !TIME write16 0xA13002 = 0x3002 (00FFFE0C) */
|
||||
/* The board probably allows up to 256MB Flash ROM remapping but this game only has 4MB ROM chip */
|
||||
if ((address & 0xfe) == 0x02)
|
||||
{
|
||||
/* upper 2MB ROM mapped to $000000-$1fffff */
|
||||
for (i=0; i<0x20; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = &cart.rom[(0x20 + i) << 16];
|
||||
}
|
||||
|
||||
/* backup RAM (8KB) mapped to $2000000-$3fffff */
|
||||
for (i=0x20; i<0x40; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = sram.sram;
|
||||
m68k.memory_map[i].read8 = sram_read_byte;
|
||||
m68k.memory_map[i].read16 = sram_read_word;
|
||||
m68k.memory_map[i].write8 = sram_write_byte;
|
||||
m68k.memory_map[i].write16 = sram_write_word;
|
||||
zbank_memory_map[i].read = sram_read_byte;
|
||||
zbank_memory_map[i].write = sram_write_byte;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
Custom ROM Bankswitch used in RADICA cartridges
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++
|
||||
Two different boards seem to exist (one with support for 64KB banks mapping and another one supporting 128KB banks + battery-RAM).
|
||||
Radica Volume 1 requires 64KB banks mapping as the menu is located at a 64KB boundary.
|
||||
Sensible Soccer Plus edition requires 128KB banks mapping with only VA6-VA2 being used to select bank index (VA1 is ignored).
|
||||
Sensible Soccer Plus edition also requires 8KB backup RAM to be mapped in higher 2MB range.
|
||||
Other games support both 64KB or 128KB mapping so it's not clear what exact board they are using but none require SRAM so we use 64KB mapper by default.
|
||||
Note that Radica Volume 3 uses similar ROM mapping as Sensible Soccer Plus edition so it might be using same 128KB board, without any SRAM chip connected.
|
||||
*/
|
||||
static uint32 mapper_radica_r(uint32 address)
|
||||
static uint32 mapper_64k_radica_r(uint32 address)
|
||||
{
|
||||
int i = 0;
|
||||
address = (address >> 1);
|
||||
|
||||
|
||||
/* 64 x 64k banks */
|
||||
for (i = 0; i < 64; i++)
|
||||
/*
|
||||
Volume 1
|
||||
--------
|
||||
000000h-0fffffh: Kid Chameleon : !TIME read16 0xA13000 (00FF103A)
|
||||
100000h-1fffffh: Dr Robotnik's Mean Bean Machine : !TIME read16 0xA13020 (00FF101E)
|
||||
200000h-27ffffh: Sonic The Hedgehog : !TIME read16 0xA13040 (00FF101E)
|
||||
280000h-2fffffh: Golden Axe : !TIME read16 0xA13050 (00FF101E)
|
||||
300000h-37ffffh: Altered Beast : !TIME read16 0xA13060 (00FF101E)
|
||||
380000h-39ffffh: Flicky : !TIME read16 0xA13070 (00FF101E)
|
||||
3a0000h-3effffh: N/A : N/A
|
||||
3f0000h-3fffffh: Radica Menu (64 KB) : !TIME read16 0xA1307E (00FF1006)
|
||||
|
||||
Volume 2
|
||||
--------
|
||||
000000h-0fffffh: Sonic The Hedgehog 2 : !TIME read16 0xA13000 (00FF103A)
|
||||
100000h-1fffffh: The Ooze : !TIME read16 0xA13020 (00FF101E)
|
||||
200000h-2fffffh: Ecco The Dolphin : !TIME read16 0xA13040 (00FF101E)
|
||||
300000h-37ffffh: Gain Ground : !TIME read16 0xA13060 (00FF101E)
|
||||
380000h-3bffffh: Alex Kidd in Enchanted Castle : !TIME read16 0xA13070 (00FF101E)
|
||||
3c0000h-3dffffh: Columns : !TIME read16 0xA13078 (00FF101E)
|
||||
3e0000h-3fffffh: Radica Menu (128 KB) : !TIME read16 0xA1307C (00FF1006)
|
||||
|
||||
Volume 3 - Super Sonic Gold edition
|
||||
-----------------------------------
|
||||
000000h-01ffffh: Radica Menu (128 KB) : N/A
|
||||
020000h-07ffffh: N/A : N/A
|
||||
080000h-0fffffh: Sonic The Hedgehog : !TIME read16 0xA13010 (00FF1012)
|
||||
100000h-1fffffh: Sonic The Hedgehog 2 : !TIME read16 0xA13020 (00FF1012)
|
||||
200000h-2fffffh: Sonic Spinball : !TIME read16 0xA13040 (00FF1012)
|
||||
300000h-3fffffh: Dr Robotnik's Mean Bean Machine : !TIME read16 0xA13060 (00FF1012)
|
||||
|
||||
Street Fighter 2 CE edition
|
||||
---------------------------
|
||||
000000h-2fffffh: Street Fighter 2 CE : !TIME read16 0xA13000 (00FF103A)
|
||||
300000h-3bffffh: Ghouls'n Ghosts : !TIME read16 0xA13060 (00FF101E)
|
||||
3c0000h-3dffffh: Radica Menu (128 KB) : !TIME read16 0xA13078 (00FF1006)
|
||||
3e0000h-3fffffh: N/A : N/A
|
||||
*/
|
||||
int index = (address >> 1) & 0x3F;
|
||||
|
||||
/* $000000-$3fffff area is mapped to selected banks (OR gates between VA21-VA16 and selected index) */
|
||||
for (i = 0x00; i < 0x40; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = &cart.rom[((address++)& 0x3f)<< 16];
|
||||
m68k.memory_map[i].base = &cart.rom[(index | i) << 16];
|
||||
}
|
||||
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
static uint32 mapper_128k_radica_r(uint32 address)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
/* 32 x 128k banks */
|
||||
/*
|
||||
Sensible Soccer Plus edition
|
||||
----------------------------
|
||||
000000h-01ffffh: Radica Menu (128 KB) : N/A
|
||||
020000h-07ffffh: N/A : N/A
|
||||
080000h-0fffffh: Sensible Soccer : !TIME read16 0xA13010 (00FF1012)
|
||||
100000h-1fffffh: Mega-Lo-Mania : !TIME read16 0xA13022 (00FF1012)
|
||||
200000h-37ffffh: Cannon Fodder : !TIME read16 0xA13042 (00FF1012)
|
||||
380000h-3fffffh: N/A : N/A
|
||||
|
||||
Note: address bit 1 is ignored for bank selection but might be used to enable/disable SRAM mapping ?
|
||||
*/
|
||||
int index = (address >> 1) & 0x3E;
|
||||
|
||||
/* $000000-$1fffff area is mapped to selected banks (OR gates between VA20-VA17 and selected index) */
|
||||
for (i = 0x00; i < 0x20; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = &cart.rom[(index | i) << 16];
|
||||
}
|
||||
|
||||
/* $200000-$3fffff area is mapped to 8KB SRAM (mirrored) */
|
||||
for (i = 0x20; i < 0x40; i++)
|
||||
{
|
||||
m68k.memory_map[i].base = sram.sram;
|
||||
m68k.memory_map[i].read8 = sram_read_byte;
|
||||
m68k.memory_map[i].read16 = sram_read_word;
|
||||
m68k.memory_map[i].write8 = sram_write_byte;
|
||||
m68k.memory_map[i].write16 = sram_write_word;
|
||||
zbank_memory_map[i].read = sram_read_byte;
|
||||
zbank_memory_map[i].write = sram_write_byte;
|
||||
}
|
||||
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
Custom logic (ST 16S25HB1 PAL) used in Micro Machines US cartridge (SR16V1.1 board)
|
||||
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
/VRES is asserted after write access to 0xA14101 (TMSS bank-shift register)
|
||||
with D0=1 (cartridge ROM access enabled instead of TMSS Boot ROM) being detected
|
||||
*/
|
||||
static void mapper_sr16v1_w(uint32 address, uint32 data)
|
||||
{
|
||||
/* 0xA10000-0xA1FFFF address range is mapped to I/O and Control registers */
|
||||
ctrl_io_write_byte(address, data);
|
||||
|
||||
/* cartridge uses /LWR, /AS and VA1-VA18 (only VA8-VA17 required to decode access to TMSS bank-shift register) */
|
||||
if ((address & 0xff01) == 0x4101)
|
||||
{
|
||||
/* cartridge ROM is enabled when D0=1 */
|
||||
if (data & 0x01)
|
||||
{
|
||||
gen_reset(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************
|
||||
default !TIME signal handler
|
||||
@@ -1675,7 +1933,7 @@ static uint32 mapper_radica_r(uint32 address)
|
||||
static void default_time_w(uint32 address, uint32 data)
|
||||
{
|
||||
/* enable multi-game cartridge mapper by default */
|
||||
if (address < 0xa13040)
|
||||
if (address < 0xa13060)
|
||||
{
|
||||
mapper_64k_multi_w(address);
|
||||
return;
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* Mega Drive cartridge hardware support
|
||||
*
|
||||
* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Most cartridge protections were initially documented by Haze
|
||||
* (http://haze.mameworld.info/)
|
||||
@@ -81,10 +81,10 @@ typedef struct
|
||||
uint32 mask; /* ROM mask */
|
||||
uint8 special; /* custom external hardware (Lock-On, J-Cart, 3-D glasses, Terebi Oekaki,...) */
|
||||
cart_hw_t hw; /* cartridge internal hardware */
|
||||
uint8 rom[MAXROMSIZE]; /* ROM area */
|
||||
uint8 lockrom[0x10000]; /* Game Genie / (Pro) Action Replay Lock-On ROM area (max 64KB) */
|
||||
uint8 rom[MAXROMSIZE]; /* cartridge ROM area */
|
||||
} md_cart_t;
|
||||
|
||||
|
||||
/* Function prototypes */
|
||||
extern void md_cart_init(void);
|
||||
extern void md_cart_reset(int hard_reset);
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* SG-1000, Master System & Game Gear cartridge hardware support
|
||||
*
|
||||
* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -39,6 +39,7 @@
|
||||
#include "shared.h"
|
||||
#include "eeprom_93c.h"
|
||||
#include "terebi_oekaki.h"
|
||||
#include "scrc32.h"
|
||||
|
||||
#define MAPPER_NONE (0x00)
|
||||
#define MAPPER_TEREBI (0x01)
|
||||
@@ -133,9 +134,12 @@ static const rominfo_t game_list[] =
|
||||
{0x5E53C7F7, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* Ernie Els Golf */
|
||||
{0xD9A7F170, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* Man Overboard! */
|
||||
{0xF7C524F6, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* Micro Machines [GG] */
|
||||
{0xC21E6CD0, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* Micro Machines [GG] [Proto] */
|
||||
{0xDBE8895C, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* Micro Machines 2 - Turbo Tournament */
|
||||
{0xC1756BEE, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* Pete Sampras Tennis */
|
||||
{0x72981057, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* CJ Elephant Fugitive */
|
||||
{0x3ACE6335, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* CJ Elephant Fugitive [Proto] */
|
||||
{0x2306AAF4, 0, 0, 0, MAPPER_CODIES, SYSTEM_GG, REGION_USA}, /* Dinobasher - Starring Bignose the Caveman [GG] [Proto] */
|
||||
|
||||
/* games using serial EEPROM */
|
||||
{0x36EBCD6D, 0, 0, 0, MAPPER_93C46, SYSTEM_GG, REGION_USA}, /* Majors Pro Baseball */
|
||||
@@ -196,6 +200,7 @@ static const rominfo_t game_list[] =
|
||||
{0xC0E25D62, 0, 0, 0, MAPPER_SEGA, SYSTEM_SMS2, REGION_EUROPE}, /* California Games II */
|
||||
{0x45C50294, 0, 0, 0, MAPPER_SEGA, SYSTEM_SMS2, REGION_EUROPE}, /* Jogos de Verao II (BR) */
|
||||
{0xC9DBF936, 0, 0, 0, MAPPER_SEGA, SYSTEM_SMS2, REGION_EUROPE}, /* Home Alone */
|
||||
{0xA109A6FE, 0, 0, 0, MAPPER_SEGA, SYSTEM_SMS2, REGION_EUROPE}, /* Power Strike II */
|
||||
{0x0047B615, 0, 0, 0, MAPPER_SEGA, SYSTEM_SMS2, REGION_EUROPE}, /* Predator2 */
|
||||
{0xF42E145C, 0, 0, 0, MAPPER_SEGA, SYSTEM_SMS2, REGION_EUROPE}, /* Quest for the Shaven Yak Starring Ren Hoek & Stimpy (BR) */
|
||||
{0x9F951756, 0, 0, 0, MAPPER_SEGA, SYSTEM_SMS2, REGION_EUROPE}, /* RoboCop 3 */
|
||||
@@ -237,6 +242,7 @@ static const rominfo_t game_list[] =
|
||||
{0xA3EF13CB, 1, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* Zaxxon 3-D */
|
||||
{0xBBA74147, 1, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* Zaxxon 3-D [Proto] */
|
||||
{0xD6F43DDA, 1, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* Out Run 3-D */
|
||||
{0x4E684EC0, 1, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* Out Run 3-D [Proto] */
|
||||
{0x871562b0, 1, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Maze Walker */
|
||||
{0x156948f9, 1, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Space Harrier 3-D (J) */
|
||||
|
||||
@@ -244,6 +250,7 @@ static const rominfo_t game_list[] =
|
||||
{0xFBE5CFBB, 1, 0, SYSTEM_LIGHTPHASER, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* Missile Defense 3D */
|
||||
{0xE79BB689, 1, 0, SYSTEM_LIGHTPHASER, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* Missile Defense 3D [BIOS] */
|
||||
{0x43DEF05D, 1, 0, SYSTEM_LIGHTPHASER, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* Missile Defense 3D [Proto] */
|
||||
{0x56DCB2D4, 1, 0, SYSTEM_LIGHTPHASER, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* 3D Gunner [Proto] */
|
||||
|
||||
/* games requiring Sega Light Phaser */
|
||||
{0x861B6E79, 0, 0, SYSTEM_LIGHTPHASER, MAPPER_SEGA, SYSTEM_SMS, REGION_USA}, /* Assault City [Light Phaser] */
|
||||
@@ -338,6 +345,8 @@ static const rominfo_t game_list[] =
|
||||
{0x56BD2455, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Doki Doki Penguin Land - Uchuu-Daibouken [Proto] */
|
||||
{0xC722FB42, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Fantasy Zone II (J) */
|
||||
{0x7ABC70E9, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Family Games (Party Games) */
|
||||
{0x9AFAB511, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Game De Check! Koutsuu Anzen [Proto] (JP) */
|
||||
{0x9E9DEB18, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Game De Check! Koutsuu Anzen [Proto] (JP) [T-Eng] */
|
||||
{0x6586BD1F, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Masters Golf */
|
||||
{0x4847BC91, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Masters Golf [Proto] */
|
||||
{0xB9FDF6D9, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Haja no Fuuin */
|
||||
@@ -350,6 +359,8 @@ static const rominfo_t game_list[] =
|
||||
{0x5B5F9106, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Nekyuu Kousien */
|
||||
{0xBEA27D5C, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Opa Opa */
|
||||
{0x6605D36A, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Phantasy Star (J) */
|
||||
{0x70E89681, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Phantasy Star (J) [T-Eng v1.02] */
|
||||
{0xA04CF71A, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Phantasy Star (J) [T-Eng v2.00] */
|
||||
{0xE1FFF1BB, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Shinobi (J) */
|
||||
{0x11645549, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Solomon no Kagi - Oujo Rihita no Namida */
|
||||
{0x7E0EF8CB, 0, 1, 0, MAPPER_SEGA, SYSTEM_SMS, REGION_JAPAN_NTSC}, /* Super Racing */
|
||||
@@ -777,11 +788,45 @@ int sms_cart_context_load(uint8 *state)
|
||||
{
|
||||
/* load Boot ROM mapper settings */
|
||||
load_param(bios_rom.fcr, 4);
|
||||
|
||||
/* set default cartridge ROM paging */
|
||||
switch (cart_rom.mapper)
|
||||
{
|
||||
case MAPPER_SEGA:
|
||||
case MAPPER_SEGA_X:
|
||||
cart_rom.fcr[0] = 0;
|
||||
cart_rom.fcr[1] = 0;
|
||||
cart_rom.fcr[2] = 1;
|
||||
cart_rom.fcr[3] = 2;
|
||||
break;
|
||||
|
||||
case MAPPER_KOREA_8K:
|
||||
case MAPPER_MSX:
|
||||
case MAPPER_MSX_NEMESIS:
|
||||
cart_rom.fcr[0] = 0;
|
||||
cart_rom.fcr[1] = 0;
|
||||
cart_rom.fcr[2] = 0;
|
||||
cart_rom.fcr[3] = 0;
|
||||
break;
|
||||
|
||||
default:
|
||||
cart_rom.fcr[0] = 0;
|
||||
cart_rom.fcr[1] = 0;
|
||||
cart_rom.fcr[2] = 1;
|
||||
cart_rom.fcr[3] = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* load cartridge mapper settings */
|
||||
load_param(cart_rom.fcr, 4);
|
||||
|
||||
/* set default BIOS ROM paging (SEGA mapper by default) */
|
||||
bios_rom.fcr[0] = 0;
|
||||
bios_rom.fcr[1] = 0;
|
||||
bios_rom.fcr[2] = 1;
|
||||
bios_rom.fcr[3] = 2;
|
||||
}
|
||||
|
||||
/* support for SG-1000 games with extra RAM */
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* SG-1000, Master System & Game Gear cartridge hardware support
|
||||
*
|
||||
* Copyright (C) 2007-2019 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* Backup RAM support
|
||||
*
|
||||
* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -37,6 +37,7 @@
|
||||
****************************************************************************************/
|
||||
|
||||
#include "shared.h"
|
||||
#include "scrc32.h"
|
||||
|
||||
T_SRAM sram;
|
||||
|
||||
@@ -61,11 +62,8 @@ T_SRAM sram;
|
||||
****************************************************************************/
|
||||
void sram_init()
|
||||
{
|
||||
memset(&sram, 0, sizeof (T_SRAM));
|
||||
|
||||
/* backup RAM data is stored above cartridge ROM area, at $800000-$80FFFF (max. 64K) */
|
||||
if (cart.romsize > 0x800000) return;
|
||||
sram.sram = cart.rom + 0x800000;
|
||||
/* disable Backup RAM by default */
|
||||
sram.detected = sram.on = sram.custom = sram.start = sram.end = 0;
|
||||
|
||||
/* initialize Backup RAM */
|
||||
if (strstr(rominfo.international,"Sonic 1 Remastered"))
|
||||
@@ -147,6 +145,13 @@ void sram_init()
|
||||
sram.start = 0x400001;
|
||||
sram.end = 0x40ffff;
|
||||
}
|
||||
else if ((rominfo.checksum == 0x0000) && (rominfo.realchecksum == 0x1f7f) && (READ_BYTE(cart.rom + 0x80000,0x1b0) == 0x52) && (READ_BYTE(cart.rom + 0x80000,0x1b1) == 0x41))
|
||||
{
|
||||
/* Radica - Sensible Soccer Plus edition (use bankswitching) */
|
||||
sram.on = 1;
|
||||
sram.start = 0x200001;
|
||||
sram.end = 0x203fff;
|
||||
}
|
||||
else if ((strstr(rominfo.ROMType,"SF") != NULL) && (strstr(rominfo.product,"001") != NULL))
|
||||
{
|
||||
/* SF-001 */
|
||||
@@ -214,8 +219,7 @@ unsigned int sram_read_byte(unsigned int address)
|
||||
|
||||
unsigned int sram_read_word(unsigned int address)
|
||||
{
|
||||
address &= 0xfffe;
|
||||
return (sram.sram[address + 1] | (sram.sram[address] << 8));
|
||||
return READ_WORD(sram.sram, address & 0xfffe);
|
||||
}
|
||||
|
||||
void sram_write_byte(unsigned int address, unsigned int data)
|
||||
@@ -225,7 +229,5 @@ void sram_write_byte(unsigned int address, unsigned int data)
|
||||
|
||||
void sram_write_word(unsigned int address, unsigned int data)
|
||||
{
|
||||
address &= 0xfffe;
|
||||
sram.sram[address] = data >> 8;
|
||||
sram.sram[address + 1] = data & 0xff;
|
||||
WRITE_WORD(sram.sram, address & 0xfffe, data);
|
||||
}
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* Backup RAM support
|
||||
*
|
||||
* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -47,7 +47,7 @@ typedef struct
|
||||
uint32 start;
|
||||
uint32 end;
|
||||
uint32 crc;
|
||||
uint8 *sram;
|
||||
uint8 sram[0x10000];
|
||||
} T_SRAM;
|
||||
|
||||
/* Function prototypes */
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* CD compatible ROM/RAM cartridge support
|
||||
*
|
||||
* Copyright (C) 2012-2016 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -38,7 +38,6 @@
|
||||
|
||||
#include "shared.h"
|
||||
|
||||
|
||||
/*--------------------------------------------------------------------------*/
|
||||
/* backup RAM cartridge (max. 512KB) */
|
||||
/*--------------------------------------------------------------------------*/
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* CD compatible ROM/RAM cartridge support
|
||||
*
|
||||
* Copyright (C) 2012-2016 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -40,7 +40,8 @@
|
||||
/* CD compatible ROM/RAM cartridge */
|
||||
typedef struct
|
||||
{
|
||||
uint8 area[0x840080]; /* cartridge ROM/RAM area (max. 8MB ROM + 64KB backup memory + Pro Action Replay 128KB ROM / 64KB RAM + cartridge infos) */
|
||||
uint8 reserved[0x80]; /* reserved for ROM cartridge infos (see md_cart.h) */
|
||||
uint8 area[0x810000]; /* cartridge ROM/RAM area (max. 8MB ROM + Pro Action Replay 64KB ROM) */
|
||||
uint8 boot; /* cartridge boot mode (0x00: boot from CD with ROM/RAM cartridge enabled, 0x40: boot from ROM cartridge with CD enabled) */
|
||||
uint8 id; /* RAM cartridge ID (related to RAM size, 0 if disabled) */
|
||||
uint8 prot; /* RAM cartridge write protection */
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/***************************************************************************************
|
||||
* Genesis Plus
|
||||
* CD data controller (LC89510 compatible)
|
||||
* CD data controller (LC8951x compatible)
|
||||
*
|
||||
* Copyright (C) 2012-2015 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2019 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -51,7 +51,6 @@
|
||||
|
||||
/* CTRL0 register bitmasks */
|
||||
#define BIT_DECEN 0x80
|
||||
#define BIT_E01RQ 0x20
|
||||
#define BIT_AUTORQ 0x10
|
||||
#define BIT_WRRQ 0x04
|
||||
|
||||
@@ -60,7 +59,7 @@
|
||||
#define BIT_FORMRQ 0x04
|
||||
#define BIT_SHDREN 0x01
|
||||
|
||||
/* CTRL2 register bitmask */
|
||||
/* STAT3 register bitmask */
|
||||
#define BIT_VALST 0x80
|
||||
|
||||
/* TODO: figure exact DMA transfer rate */
|
||||
@@ -248,7 +247,7 @@ void cdc_decoder_update(uint32 header)
|
||||
/* data decoding enabled ? */
|
||||
if (cdc.ctrl[0] & BIT_DECEN)
|
||||
{
|
||||
/* update HEAD registers */
|
||||
/* update HEADx registers with current block header */
|
||||
*(uint32 *)(cdc.head[0]) = header;
|
||||
|
||||
/* set !VALST */
|
||||
@@ -285,18 +284,50 @@ void cdc_decoder_update(uint32 header)
|
||||
/* CDC buffer address */
|
||||
offset = cdc.pt.w & 0x3fff;
|
||||
|
||||
/* write CDD block header (4 bytes) */
|
||||
/* write current block header to RAM buffer (4 bytes) */
|
||||
*(uint32 *)(cdc.ram + offset) = header;
|
||||
offset += 4;
|
||||
|
||||
/* write CDD block data (2048 bytes) */
|
||||
cdd_read_data(cdc.ram + 4 + offset);
|
||||
/* check decoded block mode */
|
||||
if (cdc.head[0][3] == 0x01)
|
||||
{
|
||||
/* write Mode 1 user data to RAM buffer (2048 bytes) */
|
||||
cdd_read_data(cdc.ram + offset, NULL);
|
||||
offset += 2048;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* check if CD-ROM Mode 2 decoding is enabled */
|
||||
if (cdc.ctrl[1] & BIT_MODRQ)
|
||||
{
|
||||
/* update HEADx registers with current block sub-header & write Mode 2 user data to RAM buffer (max 2328 bytes) */
|
||||
cdd_read_data(cdc.ram + offset + 8, cdc.head[1]);
|
||||
|
||||
/* write current block sub-header to RAM buffer (4 bytes x 2) */
|
||||
*(uint32 *)(cdc.ram + offset) = *(uint32 *)(cdc.head[1]);
|
||||
*(uint32 *)(cdc.ram + offset + 4) = *(uint32 *)(cdc.head[1]);
|
||||
offset += 2336;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* update HEADx registers with current block sub-header & write Mode 2 user data to RAM buffer (max 2328 bytes) */
|
||||
/* NB: when Mode 2 decoding is disabled, sub-header is apparently not written to RAM buffer (required by Wonder Library) */
|
||||
cdd_read_data(cdc.ram + offset, cdc.head[1]);
|
||||
offset += 2328;
|
||||
}
|
||||
|
||||
/* set STAT2 register FORM bit according to sub-header FORM bit when CTRL0 register AUTORQ bit is set */
|
||||
if (cdc.ctrl[0] & BIT_AUTORQ)
|
||||
{
|
||||
cdc.stat[2] = (cdc.ctrl[1] & BIT_MODRQ) | ((cdc.head[1][2] & 0x20) >> 3);
|
||||
}
|
||||
}
|
||||
|
||||
/* take care of buffer overrun */
|
||||
offset = offset + 2048 + 4 - 0x4000;
|
||||
if (offset > 0)
|
||||
if (offset > 0x4000)
|
||||
{
|
||||
/* data should be written at the start of buffer */
|
||||
memcpy(cdc.ram, cdc.ram + 0x4000, offset);
|
||||
memcpy(cdc.ram, cdc.ram + 0x4000, offset - 0x4000);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -484,15 +515,15 @@ void cdc_reg_w(unsigned char data)
|
||||
/* set CRCOK bit only if decoding is enabled */
|
||||
cdc.stat[0] = data & BIT_DECEN;
|
||||
|
||||
/* update decoding mode */
|
||||
/* update STAT2 register */
|
||||
if (data & BIT_AUTORQ)
|
||||
{
|
||||
/* set MODE bit according to CTRL1 register & clear FORM bit */
|
||||
cdc.stat[2] = cdc.ctrl[1] & BIT_MODRQ;
|
||||
/* set MODE bit according to CTRL1 register MODRQ bit & set FORM bit according to sub-header FORM bit*/
|
||||
cdc.stat[2] = (cdc.ctrl[1] & BIT_MODRQ) | ((cdc.head[1][2] & 0x20) >> 3);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* set MODE & FORM bits according to CTRL1 register */
|
||||
/* set MODE & FORM bits according to CTRL1 register MODRQ & FORMRQ bits */
|
||||
cdc.stat[2] = cdc.ctrl[1] & (BIT_MODRQ | BIT_FORMRQ);
|
||||
}
|
||||
|
||||
@@ -503,15 +534,15 @@ void cdc_reg_w(unsigned char data)
|
||||
|
||||
case 0x0b: /* CTRL1 */
|
||||
{
|
||||
/* update decoding mode */
|
||||
/* update STAT2 register */
|
||||
if (cdc.ctrl[0] & BIT_AUTORQ)
|
||||
{
|
||||
/* set MODE bit according to CTRL1 register & clear FORM bit */
|
||||
cdc.stat[2] = data & BIT_MODRQ;
|
||||
/* set MODE bit according to CTRL1 register MODRQ bit & set FORM bit according to sub-header FORM bit*/
|
||||
cdc.stat[2] = (data & BIT_MODRQ) | ((cdc.head[1][2] & 0x20) >> 3);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* set MODE & FORM bits according to CTRL1 register */
|
||||
/* set MODE & FORM bits according to CTRL1 register MODRQ & FORMRQ bits */
|
||||
cdc.stat[2] = data & (BIT_MODRQ | BIT_FORMRQ);
|
||||
}
|
||||
|
||||
@@ -612,7 +643,7 @@ unsigned char cdc_reg_r(void)
|
||||
|
||||
/* clear pending decoder interrupt */
|
||||
cdc.ifstat |= BIT_DECI;
|
||||
|
||||
|
||||
#if 0
|
||||
/* no pending data transfer end interrupt */
|
||||
if ((cdc.ifstat | BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN))
|
||||
@@ -639,13 +670,8 @@ unsigned short cdc_host_r(void)
|
||||
/* check if data is available */
|
||||
if (scd.regs[0x04>>1].byte.h & 0x40)
|
||||
{
|
||||
/* read data word from CDC RAM buffer */
|
||||
uint16 data = *(uint16 *)(cdc.ram + (cdc.dac.w & 0x3ffe));
|
||||
|
||||
#ifdef LSB_FIRST
|
||||
/* source data is stored in big endian format */
|
||||
data = ((data >> 8) | (data << 8)) & 0xffff;
|
||||
#endif
|
||||
/* read 16-bit word from CDC RAM buffer (big-endian format) */
|
||||
uint16 data = READ_WORD(cdc.ram, cdc.dac.w & 0x3ffe);
|
||||
|
||||
#ifdef LOG_CDC
|
||||
error("CDC host read 0x%04x -> 0x%04x (dbc=0x%x) (%X)\n", cdc.dac.w, data, cdc.dbc.w, s68k.pc);
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/***************************************************************************************
|
||||
* Genesis Plus
|
||||
* CD data controller (LC89510 compatible)
|
||||
* CD data controller (LC8951x compatible)
|
||||
*
|
||||
* Copyright (C) 2012-2015 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2019 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
+225
-172
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* CD drive processor & CD-DA fader
|
||||
*
|
||||
* Copyright (C) 2012-2019 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2021 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -47,7 +47,9 @@
|
||||
#define CD_SCAN_SPEED 30
|
||||
|
||||
/* CD tracks type (CD-DA by default) */
|
||||
#define TYPE_CDROM 0x01
|
||||
#define TYPE_AUDIO 0x00
|
||||
#define TYPE_MODE1 0x01
|
||||
#define TYPE_MODE2 0x02
|
||||
|
||||
/* BCD conversion lookup tables */
|
||||
static const uint8 lut_BCD_8[100] =
|
||||
@@ -122,14 +124,8 @@ static const uint32 toc_ffightj[29] =
|
||||
14553, 9834, 10542, 1699, 1792, 1781, 3783, 3052
|
||||
};
|
||||
|
||||
/* supported WAVE file header (16-bit stereo samples @44.1kHz) */
|
||||
static const unsigned char waveHeader[28] =
|
||||
{
|
||||
0x57,0x41,0x56,0x45,0x66,0x6d,0x74,0x20,0x10,0x00,0x00,0x00,0x01,0x00,
|
||||
0x02,0x00,0x44,0xac,0x00,0x00,0x10,0xb1,0x02,0x00,0x04,0x00,0x10,0x00
|
||||
};
|
||||
|
||||
/* supported WAVE file extensions */
|
||||
/* supported audio file extensions */
|
||||
static const char extensions[SUPPORTED_EXT][16] =
|
||||
{
|
||||
#if defined(USE_LIBTREMOR) || defined(USE_LIBVORBIS)
|
||||
@@ -319,10 +315,14 @@ int cdd_load(char *filename, char *header)
|
||||
/* open file */
|
||||
fd = cdStreamOpen(filename);
|
||||
if (!fd)
|
||||
return (-1);
|
||||
{
|
||||
/* do not return an error as this could be a ROM loaded in memory */
|
||||
/* which should be handled by load_archive function */
|
||||
return (0);
|
||||
}
|
||||
|
||||
#if defined(USE_LIBCHDR)
|
||||
if (!memcmp(".chd", &filename[strlen(filename) - 4], 4) || !memcmp(".CHD", &filename[strlen(filename) - 4], 4))
|
||||
if (!memcmp("chd", &filename[strlen(filename) - 3], 3) || !memcmp("CHD", &filename[strlen(filename) - 3], 3))
|
||||
{
|
||||
int sectors = 0;
|
||||
char metadata[256];
|
||||
@@ -400,19 +400,31 @@ int cdd_load(char *filename, char *header)
|
||||
}
|
||||
else
|
||||
{
|
||||
/* COOKED format (2048 bytes data blocks) */
|
||||
if (!strcmp(type, "MODE1"))
|
||||
cdd.sectorSize = 2048;
|
||||
|
||||
/* RAW format (2352 bytes data blocks) */
|
||||
else if (!strcmp(type, "MODE1_RAW"))
|
||||
if (!strcmp(type, "MODE1_RAW"))
|
||||
{
|
||||
/* Mode 1 RAW format (2352 bytes data blocks) */
|
||||
cdd.sectorSize = 2352;
|
||||
|
||||
/* unsupported track format */
|
||||
cdd.toc.tracks[0].type = TYPE_MODE1;
|
||||
}
|
||||
else if (!strcmp(type, "MODE1"))
|
||||
{
|
||||
/* Mode 1 COOKED format (2048 bytes data blocks) */
|
||||
cdd.sectorSize = 2048;
|
||||
cdd.toc.tracks[0].type = TYPE_MODE1;
|
||||
}
|
||||
else if (!strcmp(type, "MODE2_RAW"))
|
||||
{
|
||||
/* Mode 2 RAW format (2352 bytes data blocks) */
|
||||
cdd.sectorSize = 2352;
|
||||
cdd.toc.tracks[0].type = TYPE_MODE2;
|
||||
}
|
||||
else if (strcmp(type, "AUDIO"))
|
||||
{
|
||||
/* unsupported track format */
|
||||
break;
|
||||
|
||||
/* Data track start LBA (2s pause assumed by default) */
|
||||
}
|
||||
|
||||
/* First track start LBA (2s pause assumed by default) */
|
||||
cdd.toc.tracks[0].start = 0;
|
||||
}
|
||||
|
||||
@@ -448,9 +460,6 @@ int cdd_load(char *filename, char *header)
|
||||
|
||||
/* copy CD image header + security code (skip RAW sector 16-byte header) */
|
||||
memcpy(header, cdd.chd.hunk + (cdd.toc.tracks[0].offset % cdd.chd.hunkbytes) + ((cdd.sectorSize == 2048) ? 0 : 16), 0x210);
|
||||
|
||||
/* there is a valid DATA track */
|
||||
cdd.toc.tracks[0].type = TYPE_CDROM;
|
||||
}
|
||||
|
||||
/* valid CD image ? */
|
||||
@@ -475,44 +484,47 @@ int cdd_load(char *filename, char *header)
|
||||
strncpy(fname, filename, 256);
|
||||
|
||||
/* check loaded file extension */
|
||||
if (memcmp(".cue", &filename[strlen(filename) - 4], 4) && memcmp(".CUE", &filename[strlen(filename) - 4], 4))
|
||||
if (memcmp("cue", &filename[strlen(filename) - 3], 3) && memcmp("CUE", &filename[strlen(filename) - 3], 3))
|
||||
{
|
||||
int len;
|
||||
|
||||
static const uint8 sync[12] = {0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00};
|
||||
|
||||
/* read first 16 bytes */
|
||||
cdStreamRead(header, 0x10, 1, fd);
|
||||
|
||||
/* look for valid CD image identifier */
|
||||
/* auto-detect valid Sega CD image */
|
||||
if (!memcmp("SEGADISCSYSTEM", header, 14))
|
||||
{
|
||||
/* COOKED format (2048 bytes data blocks) */
|
||||
cdd.sectorSize = 2048;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* read next 16 bytes */
|
||||
cdStreamRead(header, 0x10, 1, fd);
|
||||
|
||||
/* look for valid CD image identifier */
|
||||
if (!memcmp("SEGADISCSYSTEM", header, 14))
|
||||
{
|
||||
/* RAW format (2352 bytes data blocks) */
|
||||
cdd.sectorSize = 2352;
|
||||
}
|
||||
}
|
||||
|
||||
/* valid CD image file ? */
|
||||
if (cdd.sectorSize)
|
||||
{
|
||||
/* read CD image header + security code */
|
||||
/* COOKED CD-ROM image (2048 bytes data blocks) */
|
||||
cdd.sectorSize = 2048;
|
||||
|
||||
/* CD-ROM Mode 1 by default */
|
||||
cdd.toc.tracks[0].type = TYPE_MODE1;
|
||||
}
|
||||
|
||||
/* auto-detect CD-ROM synchro pattern */
|
||||
else if (!memcmp(sync, header, 12))
|
||||
{
|
||||
/* RAW CD-ROM image (2352 bytes data blocks) */
|
||||
cdd.sectorSize = 2352;
|
||||
|
||||
/* auto-detect CD-ROM mode from block header (byte 15) */
|
||||
cdd.toc.tracks[0].type = header[15];
|
||||
|
||||
/* read next 16 bytes (start of user data) */
|
||||
cdStreamRead(header, 0x10, 1, fd);
|
||||
}
|
||||
|
||||
/* supported CD-ROM image file ? */
|
||||
if ((cdd.toc.tracks[0].type == TYPE_MODE1) || (cdd.toc.tracks[0].type == TYPE_MODE2))
|
||||
{
|
||||
/* read Sega CD image header + security code */
|
||||
cdStreamRead(header + 0x10, 0x200, 1, fd);
|
||||
|
||||
/* initialize first track file descriptor */
|
||||
cdd.toc.tracks[0].fd = fd;
|
||||
|
||||
/* this is a valid DATA track */
|
||||
cdd.toc.tracks[0].type = TYPE_CDROM;
|
||||
|
||||
/* DATA track end LBA (based on DATA file length) */
|
||||
cdStreamSeek(fd, 0, SEEK_END);
|
||||
cdd.toc.tracks[0].end = cdStreamTell(fd) / cdd.sectorSize;
|
||||
@@ -533,7 +545,7 @@ int cdd_load(char *filename, char *header)
|
||||
}
|
||||
else
|
||||
{
|
||||
/* this is not a CD image file */
|
||||
/* this is not a supported CD-ROM image file */
|
||||
isCDfile = 0;
|
||||
|
||||
/* close file */
|
||||
@@ -618,26 +630,26 @@ int cdd_load(char *filename, char *header)
|
||||
if (!strstr(lptr,"BINARY") && !strstr(lptr,"MOTOROLA"))
|
||||
{
|
||||
/* read file header */
|
||||
unsigned char head[28];
|
||||
cdStreamSeek(cdd.toc.tracks[cdd.toc.last].fd, 8, SEEK_SET);
|
||||
cdStreamRead(head, 28, 1, cdd.toc.tracks[cdd.toc.last].fd);
|
||||
unsigned char head[12];
|
||||
cdStreamRead(head, 12, 1, cdd.toc.tracks[cdd.toc.last].fd);
|
||||
cdStreamSeek(cdd.toc.tracks[cdd.toc.last].fd, 0, SEEK_SET);
|
||||
|
||||
/* autodetect WAVE file header (44.1KHz 16-bit stereo format only) */
|
||||
if (!memcmp(head, waveHeader, 28))
|
||||
|
||||
/* autodetect WAVE file */
|
||||
if (!memcmp(head, "RIFF", 4) && !memcmp(head + 8, "WAVE", 4))
|
||||
{
|
||||
/* look for 'data' chunk id */
|
||||
int dataOffset = 0;
|
||||
cdStreamSeek(cdd.toc.tracks[cdd.toc.last].fd, 36, SEEK_SET);
|
||||
while (cdStreamRead(head, 4, 1, cdd.toc.tracks[cdd.toc.last].fd))
|
||||
/* look for 'data' chunk */
|
||||
int chunkSize, dataOffset = 0;
|
||||
cdStreamSeek(cdd.toc.tracks[cdd.toc.last].fd, 12, SEEK_SET);
|
||||
while (cdStreamRead(head, 8, 1, cdd.toc.tracks[cdd.toc.last].fd))
|
||||
{
|
||||
if (!memcmp(head, "data", 4))
|
||||
{
|
||||
dataOffset = cdStreamTell(cdd.toc.tracks[cdd.toc.last].fd) + 4;
|
||||
dataOffset = cdStreamTell(cdd.toc.tracks[cdd.toc.last].fd);
|
||||
cdStreamSeek(cdd.toc.tracks[cdd.toc.last].fd, 0, SEEK_SET);
|
||||
break;
|
||||
}
|
||||
cdStreamSeek(cdd.toc.tracks[cdd.toc.last].fd, -2, SEEK_CUR);
|
||||
chunkSize = head[4] + (head[5] << 8) + (head[6] << 16) + (head[7] << 24);
|
||||
cdStreamSeek(cdd.toc.tracks[cdd.toc.last].fd, chunkSize, SEEK_CUR);
|
||||
}
|
||||
|
||||
/* check if 'data' chunk has not been found */
|
||||
@@ -679,42 +691,35 @@ int cdd_load(char *filename, char *header)
|
||||
/* decode TRACK commands */
|
||||
else if ((sscanf(lptr, "TRACK %02d %*s", &bb)) || (sscanf(lptr, "TRACK %d %*s", &bb)))
|
||||
{
|
||||
/* check track number */
|
||||
if (bb != (cdd.toc.last + 1))
|
||||
{
|
||||
/* close any opened file */
|
||||
if (cdd.toc.tracks[cdd.toc.last].fd)
|
||||
{
|
||||
cdStreamClose(cdd.toc.tracks[cdd.toc.last].fd);
|
||||
cdd.toc.tracks[cdd.toc.last].fd = 0;
|
||||
}
|
||||
|
||||
/* missing tracks */
|
||||
break;
|
||||
}
|
||||
|
||||
/* autodetect DATA track (first track only) */
|
||||
/* autodetect DATA track type (first track only) */
|
||||
if (!cdd.toc.last)
|
||||
{
|
||||
/* CD-ROM Mode 1 support only */
|
||||
if (strstr(lptr,"MODE1/2048"))
|
||||
{
|
||||
/* COOKED format (2048 bytes / block) */
|
||||
/* Mode 1 COOKED format (2048 bytes / block) */
|
||||
cdd.sectorSize = 2048;
|
||||
cdd.toc.tracks[0].type = TYPE_MODE1;
|
||||
}
|
||||
else if (strstr(lptr,"MODE1/2352"))
|
||||
{
|
||||
/* RAW format (2352 bytes / block) */
|
||||
/* Mode 1 RAW format (2352 bytes / block) */
|
||||
cdd.sectorSize = 2352;
|
||||
|
||||
/* skip 16-byte header */
|
||||
cdStreamSeek(cdd.toc.tracks[0].fd, 0x10, SEEK_SET);
|
||||
cdd.toc.tracks[0].type = TYPE_MODE1;
|
||||
}
|
||||
else if (strstr(lptr,"MODE2/2352"))
|
||||
{
|
||||
/* Mode 2 RAW format (2352 bytes / block) */
|
||||
cdd.sectorSize = 2352;
|
||||
cdd.toc.tracks[0].type = TYPE_MODE2;
|
||||
}
|
||||
|
||||
if (cdd.sectorSize)
|
||||
{
|
||||
/* this is a valid DATA track */
|
||||
cdd.toc.tracks[0].type = TYPE_CDROM;
|
||||
if (cdd.sectorSize == 2352)
|
||||
{
|
||||
/* skip 16-byte header */
|
||||
cdStreamSeek(cdd.toc.tracks[0].fd, 0x10, SEEK_SET);
|
||||
}
|
||||
|
||||
/* read CD image header + security code */
|
||||
cdStreamRead(header, 0x210, 1, cdd.toc.tracks[0].fd);
|
||||
@@ -757,16 +762,16 @@ int cdd_load(char *filename, char *header)
|
||||
cdd.toc.tracks[cdd.toc.last].offset += pregap * 2352;
|
||||
|
||||
/* check if a single file is used for consecutive tracks */
|
||||
if (!cdd.toc.tracks[cdd.toc.last].fd)
|
||||
if (!cdd.toc.tracks[cdd.toc.last].fd && cdd.toc.last)
|
||||
{
|
||||
/* use common file descriptor */
|
||||
cdd.toc.tracks[cdd.toc.last].fd = cdd.toc.tracks[0].fd;
|
||||
cdd.toc.tracks[cdd.toc.last].fd = cdd.toc.tracks[cdd.toc.last - 1].fd;
|
||||
|
||||
/* current track start time (based on current file absolute time + PREGAP length) */
|
||||
cdd.toc.tracks[cdd.toc.last].start = bb + ss*75 + mm*60*75 + pregap;
|
||||
|
||||
/* check if previous track end time needs to be set */
|
||||
if (cdd.toc.last && !cdd.toc.tracks[cdd.toc.last - 1].end)
|
||||
if (!cdd.toc.tracks[cdd.toc.last - 1].end)
|
||||
{
|
||||
/* set previous track end time (based on current track start time, ignoring any "PREGAP"-type pause if no INDEX00) */
|
||||
cdd.toc.tracks[cdd.toc.last - 1].end = cdd.toc.tracks[cdd.toc.last].start;
|
||||
@@ -863,7 +868,7 @@ int cdd_load(char *filename, char *header)
|
||||
/* close CUE file */
|
||||
cdStreamClose(fd);
|
||||
}
|
||||
else
|
||||
else if (cdd.toc.last)
|
||||
{
|
||||
int i, offset = 1;
|
||||
|
||||
@@ -890,26 +895,27 @@ int cdd_load(char *filename, char *header)
|
||||
/* repeat until no more valid track files can be found */
|
||||
while (fd)
|
||||
{
|
||||
/* read file HEADER */
|
||||
unsigned char head[28];
|
||||
cdStreamSeek(fd, 8, SEEK_SET);
|
||||
cdStreamRead(head, 28, 1, fd);
|
||||
/* read file header */
|
||||
unsigned char head[12];
|
||||
cdStreamRead(head, 12, 1, fd);
|
||||
cdStreamSeek(fd, 0, SEEK_SET);
|
||||
|
||||
/* check if this is a valid WAVE file (44.1KHz 16-bit stereo format only) */
|
||||
if (!memcmp(head, waveHeader, 28))
|
||||
|
||||
/* autodetect WAVE file */
|
||||
if (!memcmp(head, "RIFF", 4) && !memcmp(head + 8, "WAVE", 4))
|
||||
{
|
||||
/* look for 'data' chunk id */
|
||||
int dataOffset = 0;
|
||||
cdStreamSeek(fd, 36, SEEK_SET);
|
||||
while (cdStreamRead(head, 4, 1, fd))
|
||||
/* look for 'data' chunk */
|
||||
int chunkSize, dataOffset = 0;
|
||||
cdStreamSeek(fd, 12, SEEK_SET);
|
||||
while (cdStreamRead(head, 8, 1, fd))
|
||||
{
|
||||
if (!memcmp(head, "data", 4))
|
||||
{
|
||||
dataOffset = cdStreamTell(fd) + 4;
|
||||
dataOffset = cdStreamTell(fd);
|
||||
cdStreamSeek(fd, 0, SEEK_SET);
|
||||
break;
|
||||
}
|
||||
cdStreamSeek(fd, -2, SEEK_CUR);
|
||||
chunkSize = head[4] + (head[5] << 8) + (head[6] << 16) + (head[7] << 24);
|
||||
cdStreamSeek(fd, chunkSize, SEEK_CUR);
|
||||
}
|
||||
|
||||
/* check if 'data' chunk has not been found */
|
||||
@@ -1033,19 +1039,9 @@ int cdd_load(char *filename, char *header)
|
||||
sprintf(ptr, extensions[i], cdd.toc.last + offset);
|
||||
fd = cdStreamOpen(fname);
|
||||
}
|
||||
}
|
||||
|
||||
/* CD tracks found ? */
|
||||
if (cdd.toc.last)
|
||||
{
|
||||
/* Lead-out */
|
||||
cdd.toc.tracks[cdd.toc.last].start = cdd.toc.end;
|
||||
|
||||
/* CD mounted */
|
||||
cdd.loaded = 1;
|
||||
|
||||
/* Valid DATA track found ? */
|
||||
if (cdd.toc.tracks[0].type)
|
||||
/* Valid CD-ROM Mode 1 track found ? */
|
||||
if (cdd.toc.tracks[0].type == TYPE_MODE1)
|
||||
{
|
||||
/* simulate audio tracks if none found */
|
||||
if (cdd.toc.last == 1)
|
||||
@@ -1129,6 +1125,11 @@ int cdd_load(char *filename, char *header)
|
||||
}
|
||||
while (cdd.toc.last < 29);
|
||||
}
|
||||
else if (strstr(header + 0x180,"T-06201-01") != NULL)
|
||||
{
|
||||
/* Sewer Shark (USA) (REV1) */
|
||||
/* no audio track */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* default TOC (99 tracks & 2s per audio tracks) */
|
||||
@@ -1144,6 +1145,17 @@ int cdd_load(char *filename, char *header)
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* CD tracks found ? */
|
||||
if (cdd.toc.last)
|
||||
{
|
||||
/* Lead-out */
|
||||
cdd.toc.tracks[cdd.toc.last].start = cdd.toc.end;
|
||||
|
||||
/* CD mounted */
|
||||
cdd.loaded = 1;
|
||||
|
||||
/* Automatically try to open associated subcode data file */
|
||||
memcpy(&fname[strlen(fname) - 4], ".sub", 4);
|
||||
cdd.toc.sub = cdStreamOpen(fname);
|
||||
@@ -1215,7 +1227,7 @@ void cdd_unload(void)
|
||||
cdd.sectorSize = 0;
|
||||
}
|
||||
|
||||
void cdd_read_data(uint8 *dst)
|
||||
void cdd_read_data(uint8 *dst, uint8 *subheader)
|
||||
{
|
||||
/* only allow reading (first) CD-ROM track sectors */
|
||||
if (cdd.toc.tracks[cdd.index].type && (cdd.lba >= 0))
|
||||
@@ -1236,36 +1248,60 @@ void cdd_read_data(uint8 *dst)
|
||||
cdd.chd.hunknum = hunknum;
|
||||
}
|
||||
|
||||
/* copy Mode 1 sector data (2048 bytes only) */
|
||||
/* check sector size */
|
||||
if (cdd.sectorSize == 2048)
|
||||
{
|
||||
/* Mode 1 COOKED data (ISO) */
|
||||
/* read Mode 1 user data (2048 bytes) */
|
||||
memcpy(dst, cdd.chd.hunk + (offset % cdd.chd.hunkbytes), 2048);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Mode 1 RAW data (skip 16-byte header) */
|
||||
memcpy(dst, cdd.chd.hunk + (offset % cdd.chd.hunkbytes) + 16, 2048);
|
||||
/* check if sub-header is required (Mode 2 sector only) */
|
||||
if (!subheader)
|
||||
{
|
||||
/* read Mode 1 user data (2048 bytes), skipping block sync pattern (12 bytes) + block header (4 bytes)*/
|
||||
memcpy(dst, cdd.chd.hunk + (offset % cdd.chd.hunkbytes) + 12 + 4, 2048);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* read Mode 2 sub-header (first 4 bytes), skipping block sync pattern (12 bytes) + block header (4 bytes)*/
|
||||
memcpy(subheader, cdd.chd.hunk + (offset % cdd.chd.hunkbytes) + 12 + 4, 4);
|
||||
|
||||
/* read Mode 2 user data (max 2328 bytes), skipping Mode 2 sub-header (8 bytes) */
|
||||
memcpy(dst, cdd.chd.hunk + (offset % cdd.chd.hunkbytes) + 12 + 4 + 8, 2328);
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* seek current track sector */
|
||||
/* check sector size */
|
||||
if (cdd.sectorSize == 2048)
|
||||
{
|
||||
/* Mode 1 COOKED data (ISO) */
|
||||
/* read Mode 1 user data (2048 bytes) */
|
||||
cdStreamSeek(cdd.toc.tracks[0].fd, cdd.lba * 2048, SEEK_SET);
|
||||
cdStreamRead(dst, 2048, 1, cdd.toc.tracks[0].fd);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Mode 1 RAW data (skip 16-byte header) */
|
||||
cdStreamSeek(cdd.toc.tracks[0].fd, cdd.lba * 2352 + 16, SEEK_SET);
|
||||
}
|
||||
/* check if sub-header is required (Mode 2 sector only) */
|
||||
if (!subheader)
|
||||
{
|
||||
/* skip block sync pattern (12 bytes) + block header (4 bytes) then read Mode 1 user data (2048 bytes) */
|
||||
cdStreamSeek(cdd.toc.tracks[0].fd, (cdd.lba * 2352) + 12 + 4, SEEK_SET);
|
||||
cdStreamRead(dst, 2048, 1, cdd.toc.tracks[0].fd);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* skip block sync pattern (12 bytes) + block header (4 bytes) + Mode 2 sub-header (first 4 bytes) then read Mode 2 sub-header (last 4 bytes) */
|
||||
cdStreamSeek(cdd.toc.tracks[0].fd, (cdd.lba * 2352) + 12 + 4 + 4, SEEK_SET);
|
||||
cdStreamRead(subheader, 4, 1, cdd.toc.tracks[0].fd);
|
||||
|
||||
/* read Mode 1 sector data (2048 bytes only) */
|
||||
cdStreamRead(dst, 2048, 1, cdd.toc.tracks[0].fd);
|
||||
/* read Mode 2 user data (max 2328 bytes) */
|
||||
cdStreamRead(dst, 2328, 1, cdd.toc.tracks[0].fd);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1545,30 +1581,16 @@ void cdd_update(void)
|
||||
error("LBA = %d (track %d)(latency=%d)\n", cdd.lba, cdd.index, cdd.latency);
|
||||
#endif
|
||||
|
||||
/* seeking disc */
|
||||
if (cdd.status == CD_SEEK)
|
||||
/* drive latency */
|
||||
if (cdd.latency > 0)
|
||||
{
|
||||
/* drive latency */
|
||||
if (cdd.latency > 0)
|
||||
{
|
||||
cdd.latency--;
|
||||
return;
|
||||
}
|
||||
|
||||
/* drive is ready */
|
||||
cdd.status = CD_PAUSE;
|
||||
cdd.latency--;
|
||||
return;
|
||||
}
|
||||
|
||||
/* reading disc */
|
||||
else if (cdd.status == CD_PLAY)
|
||||
if (cdd.status == CD_PLAY)
|
||||
{
|
||||
/* drive latency */
|
||||
if (cdd.latency > 0)
|
||||
{
|
||||
cdd.latency--;
|
||||
return;
|
||||
}
|
||||
|
||||
/* end of disc detection */
|
||||
if (cdd.index >= cdd.toc.last)
|
||||
{
|
||||
@@ -1585,13 +1607,13 @@ void cdd_update(void)
|
||||
/* track type */
|
||||
if (cdd.toc.tracks[cdd.index].type)
|
||||
{
|
||||
/* CD-ROM (Mode 1) sector header */
|
||||
/* CD-ROM sector header */
|
||||
uint8 header[4];
|
||||
uint32 msf = cdd.lba + 150;
|
||||
header[0] = lut_BCD_8[(msf / 75) / 60];
|
||||
header[1] = lut_BCD_8[(msf / 75) % 60];
|
||||
header[2] = lut_BCD_8[(msf % 75)];
|
||||
header[3] = 0x01;
|
||||
header[3] = cdd.toc.tracks[cdd.index].type;
|
||||
|
||||
/* decode CD-ROM track sector */
|
||||
cdc_decoder_update(*(uint32 *)(header));
|
||||
@@ -1725,7 +1747,7 @@ void cdd_update(void)
|
||||
}
|
||||
|
||||
/* AUDIO track playing ? */
|
||||
scd.regs[0x36>>1].byte.h = cdd.toc.tracks[cdd.index].type;
|
||||
scd.regs[0x36>>1].byte.h = cdd.toc.tracks[cdd.index].type ? 0x01 : 0x00;
|
||||
|
||||
/* seek to current subcode position */
|
||||
if (cdd.toc.sub)
|
||||
@@ -1775,19 +1797,50 @@ void cdd_process(void)
|
||||
/* Process CDD command */
|
||||
switch (scd.regs[0x42>>1].byte.h & 0x0f)
|
||||
{
|
||||
case 0x00: /* Report Drive Status */
|
||||
case 0x00: /* Get Drive Status */
|
||||
{
|
||||
/* RS1-RS8 normally unchanged */
|
||||
scd.regs[0x38>>1].byte.h = cdd.status;
|
||||
|
||||
/* unless RS1 indicated invalid track infos */
|
||||
if (scd.regs[0x38>>1].byte.l == 0x0f)
|
||||
/* RS0-RS1 are normally unchanged unless reported drive status needs to be updated (i.e previous drive command has been processed) */
|
||||
/* Note: this function is called one 75hz frame ahead of CDD update so latency counter is always one step ahead of upcoming status */
|
||||
/* Radical Rex and Annet Futatabi both need at least respectively 2 and 3 interrupts with 'playing' status returned before sectors start getting incremented */
|
||||
if (cdd.latency <= 3)
|
||||
{
|
||||
/* and drive is now ready */
|
||||
if (!cdd.latency)
|
||||
/* update reported drive status */
|
||||
scd.regs[0x38>>1].byte.h = cdd.status;
|
||||
|
||||
/* check if RS1 indicated invalid track infos (during seeking) */
|
||||
if (scd.regs[0x38>>1].byte.l == 0x0f)
|
||||
{
|
||||
/* then return valid track infos, e.g current track number in RS2-RS3 (fixes Lunar - The Silver Star) */
|
||||
scd.regs[0x38>>1].byte.l = 0x02;
|
||||
/* seeking has ended so we return valid track infos, e.g current absolute time by default (fixes Lunar - The Silver Star) */
|
||||
int lba = cdd.lba + 150;
|
||||
scd.regs[0x38>>1].byte.l = 0x00;
|
||||
scd.regs[0x3a>>1].w = lut_BCD_16[(lba/75)/60];
|
||||
scd.regs[0x3c>>1].w = lut_BCD_16[(lba/75)%60];
|
||||
scd.regs[0x3e>>1].w = lut_BCD_16[(lba%75)];
|
||||
scd.regs[0x40>>1].byte.h = cdd.toc.tracks[cdd.index].type ? 0x04 : 0x00; /* Current block flags in RS8 (bit0 = mute status, bit1: pre-emphasis status, bit2: track type) */
|
||||
}
|
||||
|
||||
/* otherwise, check if RS2-RS8 need to be updated */
|
||||
else if (scd.regs[0x38>>1].byte.l == 0x00)
|
||||
{
|
||||
/* current absolute time */
|
||||
int lba = cdd.lba + 150;
|
||||
scd.regs[0x3a>>1].w = lut_BCD_16[(lba/75)/60];
|
||||
scd.regs[0x3c>>1].w = lut_BCD_16[(lba/75)%60];
|
||||
scd.regs[0x3e>>1].w = lut_BCD_16[(lba%75)];
|
||||
scd.regs[0x40>>1].byte.h = cdd.toc.tracks[cdd.index].type ? 0x04 : 0x00; /* Current block flags in RS8 (bit0 = mute status, bit1: pre-emphasis status, bit2: track type) */
|
||||
}
|
||||
else if (scd.regs[0x38>>1].byte.l == 0x01)
|
||||
{
|
||||
/* current track relative time */
|
||||
int lba = abs(cdd.lba - cdd.toc.tracks[cdd.index].start);
|
||||
scd.regs[0x3a>>1].w = lut_BCD_16[(lba/75)/60];
|
||||
scd.regs[0x3c>>1].w = lut_BCD_16[(lba/75)%60];
|
||||
scd.regs[0x3e>>1].w = lut_BCD_16[(lba%75)];
|
||||
scd.regs[0x40>>1].byte.h = cdd.toc.tracks[cdd.index].type ? 0x04 : 0x00; /* Current block flags in RS8 (bit0 = mute status, bit1: pre-emphasis status, bit2: track type) */
|
||||
}
|
||||
else if (scd.regs[0x38>>1].byte.l == 0x02)
|
||||
{
|
||||
/* current track number */
|
||||
scd.regs[0x3a>>1].w = (cdd.index < cdd.toc.last) ? lut_BCD_16[cdd.index + 1] : 0x0A0A;
|
||||
}
|
||||
}
|
||||
@@ -1824,7 +1877,7 @@ void cdd_process(void)
|
||||
scd.regs[0x3a>>1].w = lut_BCD_16[(lba/75)/60];
|
||||
scd.regs[0x3c>>1].w = lut_BCD_16[(lba/75)%60];
|
||||
scd.regs[0x3e>>1].w = lut_BCD_16[(lba%75)];
|
||||
scd.regs[0x40>>1].byte.h = cdd.toc.tracks[cdd.index].type << 2; /* Current block flags in RS8 (bit0 = mute status, bit1: pre-emphasis status, bit2: track type) */
|
||||
scd.regs[0x40>>1].byte.h = cdd.toc.tracks[cdd.index].type ? 0x04 : 0x00; /* Current block flags in RS8 (bit0 = mute status, bit1: pre-emphasis status, bit2: track type) */
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -1835,7 +1888,7 @@ void cdd_process(void)
|
||||
scd.regs[0x3a>>1].w = lut_BCD_16[(lba/75)/60];
|
||||
scd.regs[0x3c>>1].w = lut_BCD_16[(lba/75)%60];
|
||||
scd.regs[0x3e>>1].w = lut_BCD_16[(lba%75)];
|
||||
scd.regs[0x40>>1].byte.h = cdd.toc.tracks[cdd.index].type << 2; /* Current block flags in RS8 (bit0 = mute status, bit1: pre-emphasis status, bit2: track type) */
|
||||
scd.regs[0x40>>1].byte.h = cdd.toc.tracks[cdd.index].type ? 0x04 : 0x00; /* Current block flags in RS8 (bit0 = mute status, bit1: pre-emphasis status, bit2: track type) */
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -1878,7 +1931,7 @@ void cdd_process(void)
|
||||
scd.regs[0x3a>>1].w = lut_BCD_16[(lba/75)/60];
|
||||
scd.regs[0x3c>>1].w = lut_BCD_16[(lba/75)%60];
|
||||
scd.regs[0x3e>>1].w = lut_BCD_16[(lba%75)];
|
||||
scd.regs[0x3e>>1].byte.h |= (cdd.toc.tracks[track-1].type << 3); /* RS6 bit 3 is set for CD-ROM track */
|
||||
scd.regs[0x3e>>1].byte.h |= cdd.toc.tracks[track-1].type ? 0x08 : 0x00; /* RS6 bit 3 is set for CD-ROM track */
|
||||
scd.regs[0x40>>1].byte.h = track % 10; /* Track Number (low digit) */
|
||||
break;
|
||||
}
|
||||
@@ -1918,8 +1971,7 @@ void cdd_process(void)
|
||||
if (!cdd.latency)
|
||||
{
|
||||
/* Fixes a few games hanging because they expect data to be read with some delay */
|
||||
/* Radical Rex needs at least one interrupt delay */
|
||||
/* Wolf Team games (Anet Futatabi, Aisle Lord, Cobra Command, Earnest Evans, Road Avenger & Time Gal) need at least 11 interrupts delay */
|
||||
/* Wolf Team games (Annet Futatabi, Aisle Lord, Cobra Command, Earnest Evans, Road Avenger & Time Gal) need at least 11 interrupts delay */
|
||||
/* Space Adventure Cobra (2nd morgue scene) needs at least 13 interrupts delay (incl. seek time, so 11 is OK) */
|
||||
cdd.latency = 11;
|
||||
}
|
||||
@@ -1978,14 +2030,14 @@ void cdd_process(void)
|
||||
if (cdd.chd.file)
|
||||
{
|
||||
/* CHD file offset */
|
||||
cdd.chd.hunkofs = cdd.toc.tracks[cdd.index].offset + (lba * CD_FRAME_SIZE);
|
||||
cdd.chd.hunkofs = cdd.toc.tracks[index].offset + (lba * CD_FRAME_SIZE);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (cdd.toc.tracks[index].type)
|
||||
{
|
||||
/* DATA track */
|
||||
cdStreamSeek(cdd.toc.tracks[0].fd, lba * cdd.sectorSize, SEEK_SET);
|
||||
cdStreamSeek(cdd.toc.tracks[index].fd, lba * cdd.sectorSize, SEEK_SET);
|
||||
}
|
||||
#if defined(USE_LIBTREMOR) || defined(USE_LIBVORBIS)
|
||||
else if (cdd.toc.tracks[index].vf.seekable)
|
||||
@@ -2009,15 +2061,16 @@ void cdd_process(void)
|
||||
/* no audio track playing (yet) */
|
||||
scd.regs[0x36>>1].byte.h = 0x01;
|
||||
|
||||
/* update status */
|
||||
/* update status (reported to host once seeking has ended) */
|
||||
cdd.status = CD_PLAY;
|
||||
|
||||
/* RS0 should indicates seeking until drive is ready (fixes audio delay in Bari Arm) */
|
||||
/* RS1=0xf to invalidate track infos in RS2-RS8 until drive is ready (fixes Snatcher Act 2 start cutscene) */
|
||||
scd.regs[0x38>>1].w = (CD_PLAY << 8) | 0x0f;
|
||||
scd.regs[0x38>>1].w = (CD_SEEK << 8) | 0x0f;
|
||||
scd.regs[0x3a>>1].w = 0x0000;
|
||||
scd.regs[0x3c>>1].w = 0x0000;
|
||||
scd.regs[0x3e>>1].w = 0x0000;
|
||||
scd.regs[0x40>>1].w = ~(CD_PLAY + 0xf) & 0x0f;
|
||||
scd.regs[0x40>>1].w = ~(CD_SEEK + 0xf) & 0x0f;
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -2084,14 +2137,14 @@ void cdd_process(void)
|
||||
if (cdd.chd.file)
|
||||
{
|
||||
/* CHD file offset */
|
||||
cdd.chd.hunkofs = cdd.toc.tracks[cdd.index].offset + (lba * CD_FRAME_SIZE);
|
||||
cdd.chd.hunkofs = cdd.toc.tracks[index].offset + (lba * CD_FRAME_SIZE);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
if (cdd.toc.tracks[index].type)
|
||||
{
|
||||
/* DATA track */
|
||||
cdStreamSeek(cdd.toc.tracks[0].fd, lba * cdd.sectorSize, SEEK_SET);
|
||||
cdStreamSeek(cdd.toc.tracks[index].fd, lba * cdd.sectorSize, SEEK_SET);
|
||||
}
|
||||
#if defined(USE_LIBTREMOR) || defined(USE_LIBVORBIS)
|
||||
else if (cdd.toc.tracks[index].vf.seekable)
|
||||
@@ -2115,8 +2168,8 @@ void cdd_process(void)
|
||||
/* no audio track playing */
|
||||
scd.regs[0x36>>1].byte.h = 0x01;
|
||||
|
||||
/* update status */
|
||||
cdd.status = CD_SEEK;
|
||||
/* update status (reported to host once seeking has ended) */
|
||||
cdd.status = CD_PAUSE;
|
||||
|
||||
/* RS1=0xf to invalidate track infos in RS2-RS8 while seeking (fixes Final Fight CD intro when seek time is emulated) */
|
||||
scd.regs[0x38>>1].w = (CD_SEEK << 8) | 0x0f;
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* CD drive processor & CD-DA fader
|
||||
*
|
||||
* Copyright (C) 2012-2019 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -136,7 +136,7 @@ extern int cdd_context_save(uint8 *state);
|
||||
extern int cdd_context_load(uint8 *state);
|
||||
extern int cdd_load(char *filename, char *header);
|
||||
extern void cdd_unload(void);
|
||||
extern void cdd_read_data(uint8 *dst);
|
||||
extern void cdd_read_data(uint8 *dst, uint8 *subheader);
|
||||
extern void cdd_read_audio(unsigned int samples);
|
||||
extern void cdd_update(void);
|
||||
extern void cdd_process(void);
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* CD graphics processor
|
||||
*
|
||||
* Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2019 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -47,10 +47,10 @@ void word_ram_0_dma_w(unsigned int words)
|
||||
|
||||
/* CDC buffer source address */
|
||||
uint16 src_index = cdc.dac.w & 0x3ffe;
|
||||
|
||||
|
||||
/* WORD-RAM destination address*/
|
||||
uint32 dst_index = (scd.regs[0x0a>>1].w << 3) & 0x1fffe;
|
||||
|
||||
|
||||
/* update DMA destination address */
|
||||
scd.regs[0x0a>>1].w += (words >> 2);
|
||||
|
||||
@@ -60,13 +60,8 @@ void word_ram_0_dma_w(unsigned int words)
|
||||
/* DMA transfer */
|
||||
while (words--)
|
||||
{
|
||||
/* read 16-bit word from CDC buffer */
|
||||
data = *(uint16 *)(cdc.ram + src_index);
|
||||
|
||||
#ifdef LSB_FIRST
|
||||
/* source data is stored in big endian format */
|
||||
data = ((data >> 8) | (data << 8)) & 0xffff;
|
||||
#endif
|
||||
/* read 16-bit word from CDC RAM buffer (big-endian format) */
|
||||
data = READ_WORD(cdc.ram, src_index);
|
||||
|
||||
/* write 16-bit word to WORD-RAM */
|
||||
*(uint16 *)(scd.word_ram[0] + dst_index) = data ;
|
||||
@@ -85,10 +80,10 @@ void word_ram_1_dma_w(unsigned int words)
|
||||
|
||||
/* CDC buffer source address */
|
||||
uint16 src_index = cdc.dac.w & 0x3ffe;
|
||||
|
||||
|
||||
/* WORD-RAM destination address*/
|
||||
uint32 dst_index = ((scd.regs[0x0a>>1].w << 3) & 0x1fffe);
|
||||
|
||||
|
||||
/* update DMA destination address */
|
||||
scd.regs[0x0a>>1].w += (words >> 2);
|
||||
|
||||
@@ -98,13 +93,8 @@ void word_ram_1_dma_w(unsigned int words)
|
||||
/* DMA transfer */
|
||||
while (words--)
|
||||
{
|
||||
/* read 16-bit word from CDC buffer */
|
||||
data = *(uint16 *)(cdc.ram + src_index);
|
||||
|
||||
#ifdef LSB_FIRST
|
||||
/* source data is stored in big endian format */
|
||||
data = ((data >> 8) | (data << 8)) & 0xffff;
|
||||
#endif
|
||||
/* read 16-bit word from CDC RAM buffer (big-endian format) */
|
||||
data = READ_WORD(cdc.ram, src_index);
|
||||
|
||||
/* write 16-bit word to WORD-RAM */
|
||||
*(uint16 *)(scd.word_ram[1] + dst_index) = data ;
|
||||
@@ -123,10 +113,10 @@ void word_ram_2M_dma_w(unsigned int words)
|
||||
|
||||
/* CDC buffer source address */
|
||||
uint16 src_index = cdc.dac.w & 0x3ffe;
|
||||
|
||||
|
||||
/* WORD-RAM destination address*/
|
||||
uint32 dst_index = (scd.regs[0x0a>>1].w << 3) & 0x3fffe;
|
||||
|
||||
|
||||
/* update DMA destination address */
|
||||
scd.regs[0x0a>>1].w += (words >> 2);
|
||||
|
||||
@@ -136,13 +126,8 @@ void word_ram_2M_dma_w(unsigned int words)
|
||||
/* DMA transfer */
|
||||
while (words--)
|
||||
{
|
||||
/* read 16-bit word from CDC buffer */
|
||||
data = *(uint16 *)(cdc.ram + src_index);
|
||||
|
||||
#ifdef LSB_FIRST
|
||||
/* source data is stored in big endian format */
|
||||
data = ((data >> 8) | (data << 8)) & 0xffff;
|
||||
#endif
|
||||
/* read 16-bit word from CDC RAM buffer (big-endian format) */
|
||||
data = READ_WORD(cdc.ram, src_index);
|
||||
|
||||
/* write 16-bit word to WORD-RAM */
|
||||
*(uint16 *)(scd.word_ram_2M + dst_index) = data ;
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* CD graphics processor
|
||||
*
|
||||
* Copyright (C) 2012 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2019 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -201,6 +201,7 @@ typedef struct _zlib_allocator zlib_allocator;
|
||||
struct _zlib_allocator
|
||||
{
|
||||
UINT32 * allocptr[MAX_ZLIB_ALLOCS];
|
||||
UINT32 * allocptr2[MAX_ZLIB_ALLOCS];
|
||||
};
|
||||
|
||||
typedef struct _zlib_codec_data zlib_codec_data;
|
||||
@@ -220,10 +221,11 @@ struct _lzma_allocator
|
||||
void (*Free)(void *p, void *address); /* address can be 0 */
|
||||
void (*FreeSz)(void *p, void *address, size_t size); /* address can be 0 */
|
||||
uint32_t* allocptr[MAX_LZMA_ALLOCS];
|
||||
uint32_t* allocptr2[MAX_LZMA_ALLOCS];
|
||||
};
|
||||
|
||||
typedef struct _lzma_codec_data lzma_codec_data;
|
||||
struct _lzma_codec_data
|
||||
struct _lzma_codec_data
|
||||
{
|
||||
CLzmaDec decoder;
|
||||
lzma_allocator allocator;
|
||||
@@ -375,6 +377,7 @@ void lzma_allocator_init(void* p)
|
||||
|
||||
/* reset pointer list */
|
||||
memset(codec->allocptr, 0, sizeof(codec->allocptr));
|
||||
memset(codec->allocptr2, 0, sizeof(codec->allocptr2));
|
||||
codec->Alloc = lzma_fast_alloc;
|
||||
codec->Free = lzma_fast_free;
|
||||
}
|
||||
@@ -403,11 +406,16 @@ void lzma_allocator_free(void* p )
|
||||
*-------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Huge alignment values for possible SIMD optimization by compiler (NEON, SSE, AVX) */
|
||||
#define LZMA_MIN_ALIGNMENT_BITS 512
|
||||
#define LZMA_MIN_ALIGNMENT_BYTES (LZMA_MIN_ALIGNMENT_BITS / 8)
|
||||
|
||||
void *lzma_fast_alloc(void *p, size_t size)
|
||||
{
|
||||
int scan;
|
||||
uint32_t *addr;
|
||||
uint32_t *addr = NULL;
|
||||
lzma_allocator *codec = (lzma_allocator *)(p);
|
||||
uintptr_t vaddr = 0;
|
||||
|
||||
/* compute the size, rounding to the nearest 1k */
|
||||
size = (size + 0x3ff) & ~0x3ff;
|
||||
@@ -420,28 +428,37 @@ void *lzma_fast_alloc(void *p, size_t size)
|
||||
{
|
||||
/* set the low bit of the size so we don't match next time */
|
||||
*ptr |= 1;
|
||||
return ptr + 1;
|
||||
|
||||
/* return aligned address of the block */
|
||||
return codec->allocptr2[scan];
|
||||
}
|
||||
}
|
||||
|
||||
/* alloc a new one and put it into the list */
|
||||
addr = (uint32_t *)malloc(sizeof(uint8_t) * (size + sizeof(uint32_t)));
|
||||
addr = (uint32_t *)malloc(size + sizeof(uint32_t) + LZMA_MIN_ALIGNMENT_BYTES);
|
||||
if (addr==NULL)
|
||||
return NULL;
|
||||
for (scan = 0; scan < MAX_LZMA_ALLOCS; scan++)
|
||||
for (int scan = 0; scan < MAX_LZMA_ALLOCS; scan++)
|
||||
{
|
||||
if (codec->allocptr[scan] == NULL)
|
||||
{
|
||||
/* store block address */
|
||||
codec->allocptr[scan] = addr;
|
||||
|
||||
/* compute aligned address, store it */
|
||||
vaddr = (uintptr_t)addr;
|
||||
vaddr = (vaddr + sizeof(uint32_t) + (LZMA_MIN_ALIGNMENT_BYTES-1)) & (~(LZMA_MIN_ALIGNMENT_BYTES-1));
|
||||
codec->allocptr2[scan] = (uint32_t*)vaddr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* set the low bit of the size so we don't match next time */
|
||||
*addr = size | 1;
|
||||
return addr + 1;
|
||||
}
|
||||
|
||||
/* return aligned address */
|
||||
return (void*)vaddr;
|
||||
}
|
||||
|
||||
/*-------------------------------------------------
|
||||
* lzma_fast_free - fast free for lzma, which
|
||||
@@ -452,21 +469,22 @@ void *lzma_fast_alloc(void *p, size_t size)
|
||||
void lzma_fast_free(void *p, void *address)
|
||||
{
|
||||
int scan;
|
||||
uint32_t *ptr;
|
||||
lzma_allocator *codec;
|
||||
uint32_t *ptr = NULL;
|
||||
lzma_allocator *codec = NULL;
|
||||
|
||||
if (address == NULL)
|
||||
return;
|
||||
|
||||
codec = (lzma_allocator *)(p);
|
||||
|
||||
/* find the hunk */
|
||||
ptr = (uint32_t *)(address) - 1;
|
||||
ptr = (uint32_t *)address;
|
||||
for (scan = 0; scan < MAX_LZMA_ALLOCS; scan++)
|
||||
{
|
||||
if (ptr == codec->allocptr[scan])
|
||||
if (ptr == codec->allocptr2[scan])
|
||||
{
|
||||
/* clear the low bit of the size to allow matches */
|
||||
*ptr &= ~1;
|
||||
*codec->allocptr[scan] &= ~1;
|
||||
return;
|
||||
}
|
||||
}
|
||||
@@ -2458,9 +2476,14 @@ static chd_error zlib_codec_decompress(void *codec, const uint8_t *src, uint32_t
|
||||
allocates and frees memory frequently
|
||||
-------------------------------------------------*/
|
||||
|
||||
/* Huge alignment values for possible SIMD optimization by compiler (NEON, SSE, AVX) */
|
||||
#define ZLIB_MIN_ALIGNMENT_BITS 512
|
||||
#define ZLIB_MIN_ALIGNMENT_BYTES (ZLIB_MIN_ALIGNMENT_BITS / 8)
|
||||
|
||||
static voidpf zlib_fast_alloc(voidpf opaque, uInt items, uInt size)
|
||||
{
|
||||
zlib_allocator *alloc = (zlib_allocator *)opaque;
|
||||
uintptr_t paddr = 0;
|
||||
UINT32 *ptr;
|
||||
int i;
|
||||
|
||||
@@ -2475,12 +2498,14 @@ static voidpf zlib_fast_alloc(voidpf opaque, uInt items, uInt size)
|
||||
{
|
||||
/* set the low bit of the size so we don't match next time */
|
||||
*ptr |= 1;
|
||||
return ptr + 1;
|
||||
|
||||
/* return aligned block address */
|
||||
return (voidpf)(alloc->allocptr2[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* alloc a new one */
|
||||
ptr = (UINT32 *)malloc(size + sizeof(UINT32));
|
||||
ptr = (UINT32 *)malloc(size + sizeof(UINT32) + ZLIB_MIN_ALIGNMENT_BYTES);
|
||||
if (!ptr)
|
||||
return NULL;
|
||||
|
||||
@@ -2489,12 +2514,16 @@ static voidpf zlib_fast_alloc(voidpf opaque, uInt items, uInt size)
|
||||
if (!alloc->allocptr[i])
|
||||
{
|
||||
alloc->allocptr[i] = ptr;
|
||||
paddr = (((uintptr_t)ptr) + sizeof(UINT32) + (ZLIB_MIN_ALIGNMENT_BYTES-1)) & (~(ZLIB_MIN_ALIGNMENT_BYTES-1));
|
||||
alloc->allocptr2[i] = (uint32_t*)paddr;
|
||||
break;
|
||||
}
|
||||
|
||||
/* set the low bit of the size so we don't match next time */
|
||||
*ptr = size | 1;
|
||||
return ptr + 1;
|
||||
|
||||
/* return aligned block address */
|
||||
return (voidpf)paddr;
|
||||
}
|
||||
|
||||
|
||||
@@ -2506,15 +2535,15 @@ static voidpf zlib_fast_alloc(voidpf opaque, uInt items, uInt size)
|
||||
static void zlib_fast_free(voidpf opaque, voidpf address)
|
||||
{
|
||||
zlib_allocator *alloc = (zlib_allocator *)opaque;
|
||||
UINT32 *ptr = (UINT32 *)address - 1;
|
||||
UINT32 *ptr = (UINT32 *)address;
|
||||
int i;
|
||||
|
||||
/* find the hunk */
|
||||
for (i = 0; i < MAX_ZLIB_ALLOCS; i++)
|
||||
if (ptr == alloc->allocptr[i])
|
||||
if (ptr == alloc->allocptr2[i])
|
||||
{
|
||||
/* clear the low bit of the size to allow matches */
|
||||
*ptr &= ~1;
|
||||
*(alloc->allocptr[i]) &= ~1;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* Mega CD / Sega CD hardware
|
||||
*
|
||||
* Copyright (C) 2012-2019 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -101,13 +101,8 @@ void prg_ram_dma_w(unsigned int words)
|
||||
/* DMA transfer */
|
||||
while (words--)
|
||||
{
|
||||
/* read 16-bit word from CDC buffer */
|
||||
data = *(uint16 *)(cdc.ram + src_index);
|
||||
|
||||
#ifdef LSB_FIRST
|
||||
/* source data is stored in big endian format */
|
||||
data = ((data >> 8) | (data << 8)) & 0xffff;
|
||||
#endif
|
||||
/* read 16-bit word from CDC RAM buffer (big-endian format) */
|
||||
data = READ_WORD(cdc.ram, src_index);
|
||||
|
||||
/* write 16-bit word to PRG-RAM */
|
||||
*(uint16 *)(scd.prg_ram + dst_index) = data ;
|
||||
@@ -997,28 +992,6 @@ static void scd_write_byte(unsigned int address, unsigned int data)
|
||||
return;
|
||||
}
|
||||
|
||||
case 0x37: /* CDD control (controlled by BIOS, byte access only ?) */
|
||||
{
|
||||
/* CDD communication started ? */
|
||||
if ((data & 0x04) && !(scd.regs[0x37>>1].byte.l & 0x04))
|
||||
{
|
||||
/* reset CDD cycle counter */
|
||||
cdd.cycles = (scd.cycles - s68k.cycles) * 3;
|
||||
|
||||
/* set pending interrupt level 4 */
|
||||
scd.pending |= (1 << 4);
|
||||
|
||||
/* update IRQ level if interrupt is enabled */
|
||||
if (scd.regs[0x32>>1].byte.l & 0x10)
|
||||
{
|
||||
s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
|
||||
}
|
||||
}
|
||||
|
||||
scd.regs[0x37>>1].byte.l = data;
|
||||
return;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
/* SUB-CPU communication words */
|
||||
@@ -1333,6 +1306,13 @@ static void scd_write_word(unsigned int address, unsigned int data)
|
||||
return;
|
||||
}
|
||||
|
||||
case 0x36: /* CDD control */
|
||||
{
|
||||
/* only bit 2 is writable (bits [1:0] forced to 0 by default) */
|
||||
scd.regs[0x37>>1].byte.l = data & 0x04;
|
||||
return;
|
||||
}
|
||||
|
||||
case 0x4a: /* CDD command 9 (controlled by BIOS, word access only ?) */
|
||||
{
|
||||
scd.regs[0x4a>>1].w = 0;
|
||||
@@ -1584,7 +1564,6 @@ void scd_init(void)
|
||||
|
||||
void scd_reset(int hard)
|
||||
{
|
||||
/* TODO: figure what exactly is resetted when RESET bit is cleared by SUB-CPU */
|
||||
if (hard)
|
||||
{
|
||||
/* Clear all ASIC registers by default */
|
||||
@@ -1632,8 +1611,11 @@ void scd_reset(int hard)
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear only SUB-CPU side registers */
|
||||
memset(&scd.regs[0x04>>1], 0, sizeof(scd.regs) - 4);
|
||||
/* TODO: figure what exactly is reset when RESET bit is cleared by SUB-CPU */
|
||||
/* Clear only SUB-CPU side registers (communication registers are not cleared, see msu-md-sample.bin) */
|
||||
scd.regs[0x04>>1].w = 0x0000;
|
||||
scd.regs[0x0c>>1].w = 0x0000;
|
||||
memset(&scd.regs[0x30>>1], 0, sizeof(scd.regs) - 0x30);
|
||||
}
|
||||
|
||||
/* SUB-CPU side default values */
|
||||
@@ -1673,6 +1655,10 @@ void scd_reset(int hard)
|
||||
|
||||
void scd_update(unsigned int cycles)
|
||||
{
|
||||
int m68k_end_cycles;
|
||||
int s68k_run_cycles;
|
||||
int s68k_end_cycles = scd.cycles + SCYCLES_PER_LINE;
|
||||
|
||||
/* update CDC DMA transfer */
|
||||
if (cdc.dma_w)
|
||||
{
|
||||
@@ -1682,63 +1668,77 @@ void scd_update(unsigned int cycles)
|
||||
/* run both CPU in sync until end of line */
|
||||
do
|
||||
{
|
||||
m68k_run(cycles);
|
||||
s68k_run(scd.cycles + SCYCLES_PER_LINE);
|
||||
}
|
||||
while ((m68k.cycles < cycles) || (s68k.cycles < (scd.cycles + SCYCLES_PER_LINE)));
|
||||
/* CD hardware remaining cycles until end of line */
|
||||
s68k_run_cycles = s68k_end_cycles - scd.cycles;
|
||||
|
||||
/* increment CD hardware cycle counter */
|
||||
scd.cycles += SCYCLES_PER_LINE;
|
||||
|
||||
/* CDD processing at 75Hz (one clock = 12500000/75 = 500000/3 CPU clocks) */
|
||||
cdd.cycles += (SCYCLES_PER_LINE * 3);
|
||||
if (cdd.cycles >= (500000 * 4))
|
||||
{
|
||||
/* reload CDD cycle counter */
|
||||
cdd.cycles -= (500000 * 4);
|
||||
|
||||
/* update CDD sector */
|
||||
cdd_update();
|
||||
|
||||
/* check if a new CDD command has been processed */
|
||||
if (!(scd.regs[0x4a>>1].byte.l & 0xf0))
|
||||
/* check Timer interrupt occurence */
|
||||
if ((scd.timer > 0) && (scd.timer < s68k_run_cycles))
|
||||
{
|
||||
/* reset CDD command wait flag */
|
||||
scd.regs[0x4a>>1].byte.l = 0xf0;
|
||||
/* adjust Sub-CPU and Main-CPU end cycle counters up to Timer interrupt occurence */
|
||||
s68k_run_cycles = scd.timer;
|
||||
m68k_end_cycles = mcycles_vdp + ((s68k_run_cycles * MCYCLES_PER_LINE) / SCYCLES_PER_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* default Main-CPU end cycle counter (end of line) */
|
||||
m68k_end_cycles = cycles;
|
||||
}
|
||||
|
||||
/* pending level 4 interrupt */
|
||||
scd.pending |= (1 << 4);
|
||||
/* run both CPU in sync until required cycle counters */
|
||||
m68k_run(m68k_end_cycles);
|
||||
s68k_run(scd.cycles + s68k_run_cycles);
|
||||
|
||||
/* level 4 interrupt enabled */
|
||||
if (scd.regs[0x32>>1].byte.l & 0x10)
|
||||
/* increment CD hardware cycle counter */
|
||||
scd.cycles += s68k_run_cycles;
|
||||
|
||||
/* CDD processing at 75Hz (one clock = 12500000/75 = 500000/3 CPU clocks) */
|
||||
cdd.cycles += (s68k_run_cycles * 3);
|
||||
if (cdd.cycles >= (500000 * 4))
|
||||
{
|
||||
/* reload CDD cycle counter */
|
||||
cdd.cycles -= (500000 * 4);
|
||||
|
||||
/* update CDD sector */
|
||||
cdd_update();
|
||||
|
||||
/* check if CDD communication is enabled */
|
||||
if (scd.regs[0x37>>1].byte.l & 0x04)
|
||||
{
|
||||
/* update IRQ level */
|
||||
s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Timer */
|
||||
if (scd.timer)
|
||||
{
|
||||
/* decrement timer */
|
||||
scd.timer -= SCYCLES_PER_LINE;
|
||||
if (scd.timer <= 0)
|
||||
{
|
||||
/* reload timer (one timer clock = 384 CPU cycles) */
|
||||
scd.timer += (scd.regs[0x30>>1].byte.l * TIMERS_SCYCLES_RATIO);
|
||||
|
||||
/* level 3 interrupt enabled ? */
|
||||
if (scd.regs[0x32>>1].byte.l & 0x08)
|
||||
{
|
||||
/* trigger level 3 interrupt */
|
||||
scd.pending |= (1 << 3);
|
||||
|
||||
/* update IRQ level */
|
||||
s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
|
||||
/* pending level 4 interrupt */
|
||||
scd.pending |= (1 << 4);
|
||||
|
||||
/* level 4 interrupt enabled */
|
||||
if (scd.regs[0x32>>1].byte.l & 0x10)
|
||||
{
|
||||
/* update IRQ level */
|
||||
s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Timer */
|
||||
if (scd.timer)
|
||||
{
|
||||
/* decrement timer */
|
||||
scd.timer -= s68k_run_cycles;
|
||||
if (scd.timer <= 0)
|
||||
{
|
||||
/* reload timer (one timer clock = 384 CPU cycles) */
|
||||
scd.timer += (scd.regs[0x30>>1].byte.l * TIMERS_SCYCLES_RATIO);
|
||||
|
||||
/* level 3 interrupt enabled ? */
|
||||
if (scd.regs[0x32>>1].byte.l & 0x08)
|
||||
{
|
||||
/* trigger level 3 interrupt */
|
||||
scd.pending |= (1 << 3);
|
||||
|
||||
/* update IRQ level */
|
||||
s68k_update_irq((scd.pending & scd.regs[0x32>>1].byte.l) >> 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
while ((m68k.cycles < cycles) || (s68k.cycles < s68k_end_cycles));
|
||||
|
||||
/* GFX processing */
|
||||
if (scd.regs[0x58>>1].byte.h & 0x80)
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* Mega CD / Sega CD hardware
|
||||
*
|
||||
* Copyright (C) 2012-2019 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2012-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
* Support for SG-1000, Mark-III, Master System, Game Gear, Mega Drive & Mega CD hardware
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2018 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -279,10 +279,18 @@ void gen_reset(int hard_reset)
|
||||
/* reset CD hardware */
|
||||
scd_reset(1);
|
||||
}
|
||||
|
||||
/* reset MD cartridge hardware (only when booting from cartridge) */
|
||||
if (scd.cartridge.boot)
|
||||
{
|
||||
md_cart_reset(hard_reset);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* reset MD cartridge hardware */
|
||||
md_cart_reset(hard_reset);
|
||||
}
|
||||
|
||||
/* reset MD cartridge hardware */
|
||||
md_cart_reset(hard_reset);
|
||||
|
||||
/* Z80 bus is released & Z80 is reseted */
|
||||
m68k.memory_map[0xa0].read8 = m68k_read_bus_8;
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
* Support for SG-1000, Mark-III, Master System, Game Gear, Mega Drive & Mega CD hardware
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2018 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* ROM Loading Support
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2018 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -647,7 +647,9 @@ int load_rom(char *filename)
|
||||
|
||||
/* auto-detect byte-swapped dumps */
|
||||
if (!memcmp((char *)(cart.rom + 0x100),"ESAGM GE ARDVI E", 16) ||
|
||||
!memcmp((char *)(cart.rom + 0x100),"ESAGG NESESI", 12))
|
||||
!memcmp((char *)(cart.rom + 0x100),"ESAGG NESESI", 12) ||
|
||||
!memcmp((char *)(cart.rom + 0x80000 + 0x100),"ESAGM GE ARDVI E", 16) ||
|
||||
!memcmp((char *)(cart.rom + 0x80000 + 0x100),"ESAGG NESESI", 12))
|
||||
{
|
||||
for(i = 0; i < size; i += 2)
|
||||
{
|
||||
@@ -1076,7 +1078,8 @@ void get_region(char *romheader)
|
||||
(strstr(rominfo.product,"T-69046-50") != NULL) || /* Back to the Future III (Europe) */
|
||||
(strstr(rominfo.product,"T-120106-00") != NULL) || /* Brian Lara Cricket (Europe) */
|
||||
(strstr(rominfo.product,"T-97126 -50") != NULL) || /* Williams Arcade's Greatest Hits (Europe) */
|
||||
(strstr(rominfo.product,"T-70096 -00") != NULL)) /* Muhammad Ali Heavyweight Boxing (Europe) */
|
||||
(strstr(rominfo.product,"T-70096 -00") != NULL) || /* Muhammad Ali Heavyweight Boxing (Europe) */
|
||||
((rominfo.checksum == 0x0000) && (rominfo.realchecksum == 0x1f7f))) /* Radica - Sensible Soccer Plus edition */
|
||||
{
|
||||
/* need PAL settings */
|
||||
region_code = REGION_EUROPE;
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* ROM Loading Support
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2018 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -188,7 +188,8 @@ void m68k_set_fc_callback(void (*callback)(unsigned int new_fc))
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef LOGVDP
|
||||
#ifdef LOGERROR
|
||||
|
||||
extern void error(char *format, ...);
|
||||
extern uint16 v_counter;
|
||||
#endif
|
||||
@@ -202,8 +203,8 @@ void m68k_update_irq(unsigned int mask)
|
||||
/* Update IRQ level */
|
||||
CPU_INT_LEVEL |= (mask << 8);
|
||||
|
||||
#ifdef LOGVDP
|
||||
error("[%d(%d)][%d(%d)] IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
|
||||
#ifdef LOGERROR
|
||||
error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -212,8 +213,8 @@ void m68k_set_irq(unsigned int int_level)
|
||||
/* Set IRQ level */
|
||||
CPU_INT_LEVEL = int_level << 8;
|
||||
|
||||
#ifdef LOGVDP
|
||||
error("[%d(%d)][%d(%d)] IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
|
||||
#ifdef LOGERROR
|
||||
error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -245,8 +246,8 @@ void m68k_set_irq_delay(unsigned int int_level)
|
||||
CPU_INT_LEVEL = int_level << 8;
|
||||
}
|
||||
|
||||
#ifdef LOGVDP
|
||||
error("[%d(%d)][%d(%d)] IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
|
||||
#ifdef LOGERROR
|
||||
error("[%d(%d)][%d(%d)] m68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, m68k.cycles/3420, m68k.cycles, m68k.cycles%3420,CPU_INT_LEVEL>>8,FLAG_INT_MASK,m68k_get_reg(M68K_REG_PC));
|
||||
#endif
|
||||
|
||||
/* Check interrupt mask to process IRQ */
|
||||
@@ -277,7 +278,7 @@ void m68k_run(unsigned int cycles)
|
||||
/* Return point for when we have an address error (TODO: use goto) */
|
||||
m68ki_set_address_error_trap() /* auto-disable (see m68kcpu.h) */
|
||||
|
||||
#ifdef LOGVDP
|
||||
#ifdef LOGERROR
|
||||
error("[%d][%d] m68k run to %d cycles (%x), irq mask = %x (%x)\n", v_counter, m68k.cycles, cycles, m68k.pc,FLAG_INT_MASK, CPU_INT_LEVEL);
|
||||
#endif
|
||||
|
||||
|
||||
@@ -40,7 +40,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 20*7, 20*7, 20*7, 20*7, 20*7, 20*7, 20*7, 20*7,
|
||||
22*7, 22*7, 22*7, 22*7, 22*7, 22*7, 22*7, 22*7, 20*7, 24*7, 0*7, 0*7, 20*7, 0*7, 0*7, 0*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7, 28*7,
|
||||
30*7, 30*7, 30*7, 30*7, 30*7, 30*7, 30*7, 30*7, 32*7, 32*7, 32*7, 32*7, 32*7, 32*7, 32*7, 32*7,
|
||||
34*7, 34*7, 34*7, 34*7, 34*7, 34*7, 34*7, 34*7, 32*7, 36*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1197,9 +1197,9 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7,
|
||||
20*7, 20*7, 20*7, 20*7, 20*7, 20*7, 20*7, 20*7, 22*7, 22*7, 22*7, 22*7, 22*7, 22*7, 22*7, 22*7,
|
||||
24*7, 24*7, 24*7, 24*7, 24*7, 24*7, 24*7, 24*7, 22*7, 26*7, 0*7, 0*7, 4*7, 0*7, 0*7, 0*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7,
|
||||
16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7,
|
||||
20*7, 20*7, 20*7, 20*7, 20*7, 20*7, 20*7, 20*7, 18*7, 22*7, 0*7, 0*7, 4*7, 0*7, 0*7, 0*7,
|
||||
0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1284,7 +1284,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7,
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1316,7 +1316,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7,
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1348,7 +1348,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7,
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1380,7 +1380,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7,
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1412,7 +1412,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7,
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1444,7 +1444,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7,
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1476,7 +1476,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7,
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
@@ -1508,7 +1508,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7,
|
||||
4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 4*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7, 8*7,
|
||||
12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7, 12*7,
|
||||
14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 14*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7, 16*7,
|
||||
18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 18*7, 16*7, 20*7, 0*7, 0*7, 0*7, 0*7, 0*7, 0*7,
|
||||
|
||||
@@ -8117,7 +8117,7 @@ static void m68k_op_divu_16_d(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8148,7 +8148,7 @@ static void m68k_op_divu_16_ai(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8179,7 +8179,7 @@ static void m68k_op_divu_16_pi(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 *10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8210,7 +8210,7 @@ static void m68k_op_divu_16_pd(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8241,7 +8241,7 @@ static void m68k_op_divu_16_di(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8272,7 +8272,7 @@ static void m68k_op_divu_16_ix(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8303,7 +8303,7 @@ static void m68k_op_divu_16_aw(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8334,7 +8334,7 @@ static void m68k_op_divu_16_al(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8365,7 +8365,7 @@ static void m68k_op_divu_16_pcdi(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8396,7 +8396,7 @@ static void m68k_op_divu_16_pcix(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -8427,7 +8427,7 @@ static void m68k_op_divu_16_i(void)
|
||||
*r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
|
||||
return;
|
||||
}
|
||||
USE_CYCLES(7 * 10);
|
||||
USE_CYCLES(MUL * 10);
|
||||
FLAG_V = VFLAG_SET;
|
||||
FLAG_N = NFLAG_SET; /* undocumented behavior (fixes Blood Shot on Genesis) */
|
||||
FLAG_C = CFLAG_CLEAR;
|
||||
@@ -23888,7 +23888,7 @@ static const opcode_handler_struct m68k_opcode_handler_table[] =
|
||||
{m68k_op_addq_8_di , 0xf1f8, 0x5028, 16},
|
||||
{m68k_op_addq_8_ix , 0xf1f8, 0x5030, 18},
|
||||
{m68k_op_addq_16_d , 0xf1f8, 0x5040, 4},
|
||||
{m68k_op_addq_16_a , 0xf1f8, 0x5048, 4},
|
||||
{m68k_op_addq_16_a , 0xf1f8, 0x5048, 8}, /* see Yacht.txt */
|
||||
{m68k_op_addq_16_ai , 0xf1f8, 0x5050, 12},
|
||||
{m68k_op_addq_16_pi , 0xf1f8, 0x5058, 12},
|
||||
{m68k_op_addq_16_pd , 0xf1f8, 0x5060, 14},
|
||||
@@ -24598,7 +24598,7 @@ static const opcode_handler_struct m68k_opcode_handler_table[] =
|
||||
{m68k_op_andi_16_pd , 0xfff8, 0x0260, 18},
|
||||
{m68k_op_andi_16_di , 0xfff8, 0x0268, 20},
|
||||
{m68k_op_andi_16_ix , 0xfff8, 0x0270, 22},
|
||||
{m68k_op_andi_32_d , 0xfff8, 0x0280, 14},
|
||||
{m68k_op_andi_32_d , 0xfff8, 0x0280, 16}, /* see Yacht.txt */
|
||||
{m68k_op_andi_32_ai , 0xfff8, 0x0290, 28},
|
||||
{m68k_op_andi_32_pi , 0xfff8, 0x0298, 28},
|
||||
{m68k_op_andi_32_pd , 0xfff8, 0x02a0, 30},
|
||||
@@ -24881,11 +24881,11 @@ static const opcode_handler_struct m68k_opcode_handler_table[] =
|
||||
{m68k_op_tst_32_di , 0xfff8, 0x4aa8, 16},
|
||||
{m68k_op_tst_32_ix , 0xfff8, 0x4ab0, 18},
|
||||
{m68k_op_tas_8_d , 0xfff8, 0x4ac0, 4},
|
||||
{m68k_op_tas_8_ai , 0xfff8, 0x4ad0, 18},
|
||||
{m68k_op_tas_8_pi , 0xfff8, 0x4ad8, 18},
|
||||
{m68k_op_tas_8_pd , 0xfff8, 0x4ae0, 20},
|
||||
{m68k_op_tas_8_di , 0xfff8, 0x4ae8, 22},
|
||||
{m68k_op_tas_8_ix , 0xfff8, 0x4af0, 24},
|
||||
{m68k_op_tas_8_ai , 0xfff8, 0x4ad0, 14}, /* see Yacht.txt */
|
||||
{m68k_op_tas_8_pi , 0xfff8, 0x4ad8, 14}, /* see Yacht.txt */
|
||||
{m68k_op_tas_8_pd , 0xfff8, 0x4ae0, 16}, /* see Yacht.txt */
|
||||
{m68k_op_tas_8_di , 0xfff8, 0x4ae8, 18}, /* see Yacht.txt */
|
||||
{m68k_op_tas_8_ix , 0xfff8, 0x4af0, 20}, /* see Yacht.txt */
|
||||
{m68k_op_movem_16_er_ai , 0xfff8, 0x4c90, 12},
|
||||
{m68k_op_movem_16_er_pi , 0xfff8, 0x4c98, 12},
|
||||
{m68k_op_movem_16_er_di , 0xfff8, 0x4ca8, 16},
|
||||
@@ -25245,10 +25245,10 @@ static const opcode_handler_struct m68k_opcode_handler_table[] =
|
||||
{m68k_op_tst_16_al , 0xffff, 0x4a79, 16},
|
||||
{m68k_op_tst_32_aw , 0xffff, 0x4ab8, 16},
|
||||
{m68k_op_tst_32_al , 0xffff, 0x4ab9, 20},
|
||||
{m68k_op_tas_8_pi7 , 0xffff, 0x4adf, 18},
|
||||
{m68k_op_tas_8_pd7 , 0xffff, 0x4ae7, 20},
|
||||
{m68k_op_tas_8_aw , 0xffff, 0x4af8, 22},
|
||||
{m68k_op_tas_8_al , 0xffff, 0x4af9, 26},
|
||||
{m68k_op_tas_8_pi7 , 0xffff, 0x4adf, 14}, /* see Yacht.txt */
|
||||
{m68k_op_tas_8_pd7 , 0xffff, 0x4ae7, 16}, /* see Yacht.txt */
|
||||
{m68k_op_tas_8_aw , 0xffff, 0x4af8, 18}, /* see Yacht.txt */
|
||||
{m68k_op_tas_8_al , 0xffff, 0x4af9, 22}, /* see Yacht.txt */
|
||||
{m68k_op_illegal , 0xffff, 0x4afc, 4},
|
||||
{m68k_op_movem_16_er_aw , 0xffff, 0x4cb8, 16},
|
||||
{m68k_op_movem_16_er_al , 0xffff, 0x4cb9, 20},
|
||||
|
||||
@@ -213,7 +213,7 @@ void s68k_update_irq(unsigned int mask)
|
||||
CPU_INT_LEVEL = mask << 8;
|
||||
|
||||
#ifdef LOG_SCD
|
||||
error("[%d][%d] IRQ Level = %d(0x%02x) (%x)\n", v_counter, s68k.cycles, CPU_INT_LEVEL>>8,FLAG_INT_MASK,s68k.pc);
|
||||
error("[%d][%d] s68k IRQ Level = %d(0x%02x) (%x)\n", v_counter, s68k.cycles, CPU_INT_LEVEL>>8,FLAG_INT_MASK,s68k.pc);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@@ -40,7 +40,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 20*4, 20*4, 20*4, 20*4, 20*4, 20*4, 20*4, 20*4,
|
||||
22*4, 22*4, 22*4, 22*4, 22*4, 22*4, 22*4, 22*4, 20*4, 24*4, 0*4, 0*4, 20*4, 0*4, 0*4, 0*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4, 28*4,
|
||||
30*4, 30*4, 30*4, 30*4, 30*4, 30*4, 30*4, 30*4, 32*4, 32*4, 32*4, 32*4, 32*4, 32*4, 32*4, 32*4,
|
||||
34*4, 34*4, 34*4, 34*4, 34*4, 34*4, 34*4, 34*4, 32*4, 36*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -243,7 +243,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
6*4, 6*4, 6*4, 6*4, 6*4, 6*4, 6*4, 6*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
10*4, 10*4, 10*4, 10*4, 10*4, 10*4, 10*4, 10*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 12*4, 16*4, 12*4, 14*4, 8*4, 10*4, 0*4, 0*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 12*4, 16*4, 12*4, 14*4, 10*4, 0*4, 0*4, 0*4,
|
||||
8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 24*4, 24*4, 24*4, 24*4, 24*4, 24*4, 24*4, 24*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
@@ -1197,9 +1197,9 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4,
|
||||
20*4, 20*4, 20*4, 20*4, 20*4, 20*4, 20*4, 20*4, 22*4, 22*4, 22*4, 22*4, 22*4, 22*4, 22*4, 22*4,
|
||||
24*4, 24*4, 24*4, 24*4, 24*4, 24*4, 24*4, 24*4, 22*4, 26*4, 0*4, 0*4, 4*4, 0*4, 0*4, 0*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4,
|
||||
16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4,
|
||||
20*4, 20*4, 20*4, 20*4, 20*4, 20*4, 20*4, 20*4, 18*4, 22*4, 0*4, 0*4, 4*4, 0*4, 0*4, 0*4,
|
||||
0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -1284,7 +1284,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -1316,7 +1316,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -1348,7 +1348,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -1380,7 +1380,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -1412,7 +1412,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -1444,7 +1444,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -1476,7 +1476,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
@@ -1508,7 +1508,7 @@ static const unsigned char m68ki_cycles[0x10000] =
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4,
|
||||
4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 4*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4, 8*4,
|
||||
12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4, 12*4,
|
||||
14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 14*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4, 16*4,
|
||||
18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 18*4, 16*4, 20*4, 0*4, 0*4, 0*4, 0*4, 0*4, 0*4,
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* Z80 bank access to 68k bus
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -39,6 +39,9 @@
|
||||
|
||||
#include "shared.h"
|
||||
|
||||
|
||||
t_zbank_memory_map zbank_memory_map[256];
|
||||
|
||||
/*
|
||||
Handlers for access to unused addresses and those which make the
|
||||
machine lock up.
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* Z80 bank access to 68k bus
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -49,10 +49,12 @@ extern void zbank_write_ctrl_io(unsigned int address, unsigned int data);
|
||||
extern unsigned int zbank_read_vdp(unsigned int address);
|
||||
extern void zbank_write_vdp(unsigned int address, unsigned int data);
|
||||
|
||||
struct _zbank_memory_map
|
||||
typedef struct
|
||||
{
|
||||
unsigned int (*read)(unsigned int address);
|
||||
void (*write)(unsigned int address, unsigned int data);
|
||||
} zbank_memory_map[256];
|
||||
} t_zbank_memory_map;
|
||||
|
||||
extern t_zbank_memory_map zbank_memory_map[256];
|
||||
|
||||
#endif /* _MEMBNK_H_ */
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
* Support for SG-1000, Mark-III, Master System, Game Gear & Mega Drive ports access
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -111,6 +111,8 @@ unsigned char z80_memory_r(unsigned int address)
|
||||
{
|
||||
if ((address >> 8) == 0x7F)
|
||||
{
|
||||
/* average Z80 wait-states when accessing 68k area */
|
||||
Z80.cycles += 3 * 15;
|
||||
return (*zbank_memory_map[0xc0].read)(address);
|
||||
}
|
||||
return z80_unused_r(address);
|
||||
@@ -118,6 +120,9 @@ unsigned char z80_memory_r(unsigned int address)
|
||||
|
||||
default: /* $8000-$FFFF: 68k bank (32K) */
|
||||
{
|
||||
/* average Z80 wait-states when accessing 68k area */
|
||||
Z80.cycles += 3 * 15;
|
||||
|
||||
address = zbank | (address & 0x7FFF);
|
||||
if (zbank_memory_map[address >> 16].read)
|
||||
{
|
||||
@@ -158,6 +163,8 @@ void z80_memory_w(unsigned int address, unsigned char data)
|
||||
|
||||
case 0x7F: /* $7F00-$7FFF: VDP */
|
||||
{
|
||||
/* average Z80 wait-states when accessing 68k area */
|
||||
Z80.cycles += 3 * 15;
|
||||
(*zbank_memory_map[0xc0].write)(address, data);
|
||||
return;
|
||||
}
|
||||
@@ -172,6 +179,9 @@ void z80_memory_w(unsigned int address, unsigned char data)
|
||||
|
||||
default: /* $8000-$FFFF: 68k bank (32K) */
|
||||
{
|
||||
/* average Z80 wait-states when accessing 68k area */
|
||||
Z80.cycles += 3 * 15;
|
||||
|
||||
address = zbank | (address & 0x7FFF);
|
||||
if (zbank_memory_map[address >> 16].write)
|
||||
{
|
||||
@@ -300,7 +310,7 @@ unsigned char z80_md_port_r(unsigned int port)
|
||||
/* read FM chip if enabled */
|
||||
if ((port >= 0xF0) && (config.ym2413 & 1))
|
||||
{
|
||||
return YM2413Read();
|
||||
return fm_read(Z80.cycles, port);
|
||||
}
|
||||
|
||||
return z80_unused_port_r(port);
|
||||
@@ -578,7 +588,7 @@ unsigned char z80_ms_port_r(unsigned int port)
|
||||
/* read FM board if enabled */
|
||||
if (!(port & 4) && (config.ym2413 & 1))
|
||||
{
|
||||
data = YM2413Read();
|
||||
data = fm_read(Z80.cycles, port);
|
||||
}
|
||||
|
||||
/* read I/O ports if enabled */
|
||||
@@ -678,7 +688,7 @@ unsigned char z80_m3_port_r(unsigned int port)
|
||||
if (!(port & 4) && (config.ym2413 & 1))
|
||||
{
|
||||
/* I/O ports are automatically disabled by hardware */
|
||||
return YM2413Read();
|
||||
return fm_read(Z80.cycles, port);
|
||||
}
|
||||
|
||||
/* read I/O ports */
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
* Support for SG-1000, Mark-III, Master System, Game Gear & Mega Drive ports access
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2016 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
@@ -28,6 +28,9 @@
|
||||
#ifdef HAVE_YM3438_CORE
|
||||
#include "ym3438.h"
|
||||
#endif
|
||||
#ifdef HAVE_OPLL_CORE
|
||||
#include "opll.h"
|
||||
#endif
|
||||
#include "sram.h"
|
||||
#include "ggenie.h"
|
||||
#include "areplay.h"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Copyright (C) 2019 Nuke.YKT
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions may not be sold, nor may they be used in a commercial
|
||||
* product or activity.
|
||||
*
|
||||
* - Redistributions that are modified from the original source must include the
|
||||
* complete source code, including the source code for all components used by a
|
||||
* binary built from the modified sources. However, as a special exception, the
|
||||
* source code distributed need not include anything that is normally distributed
|
||||
* (in either source or binary form) with the major components (compiler, kernel,
|
||||
* and so on) of the operating system on which the executable runs, unless that
|
||||
* component itself accompanies the executable.
|
||||
*
|
||||
* - Redistributions must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or other
|
||||
* materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*
|
||||
* Yamaha YM2413 emulator
|
||||
* Thanks:
|
||||
* siliconpr0n.org(digshadow, John McMaster):
|
||||
* VRC VII decap and die shot.
|
||||
*
|
||||
* version: 1.0
|
||||
*/
|
||||
|
||||
#ifndef OPLL_H
|
||||
#define OPLL_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
enum {
|
||||
opll_type_ym2413 = 0x00, /* Yamaha YM2413 */
|
||||
opll_type_ds1001, /* Konami VRC VII */
|
||||
opll_type_ym2413b /* Yamaha YM2413B */
|
||||
};
|
||||
|
||||
enum {
|
||||
opll_patch_1 = 0x00,
|
||||
opll_patch_2,
|
||||
opll_patch_3,
|
||||
opll_patch_4,
|
||||
opll_patch_5,
|
||||
opll_patch_6,
|
||||
opll_patch_7,
|
||||
opll_patch_8,
|
||||
opll_patch_9,
|
||||
opll_patch_10,
|
||||
opll_patch_11,
|
||||
opll_patch_12,
|
||||
opll_patch_13,
|
||||
opll_patch_14,
|
||||
opll_patch_15,
|
||||
opll_patch_drum_0,
|
||||
opll_patch_drum_1,
|
||||
opll_patch_drum_2,
|
||||
opll_patch_drum_3,
|
||||
opll_patch_drum_4,
|
||||
opll_patch_drum_5,
|
||||
opll_patch_max
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
uint8_t tl;
|
||||
uint8_t dc;
|
||||
uint8_t dm;
|
||||
uint8_t fb;
|
||||
uint8_t am[2];
|
||||
uint8_t vib[2];
|
||||
uint8_t et[2];
|
||||
uint8_t ksr[2];
|
||||
uint8_t multi[2];
|
||||
uint8_t ksl[2];
|
||||
uint8_t ar[2];
|
||||
uint8_t dr[2];
|
||||
uint8_t sl[2];
|
||||
uint8_t rr[2];
|
||||
} opll_patch_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t chip_type;
|
||||
uint32_t cycles;
|
||||
uint32_t slot;
|
||||
const opll_patch_t *patchrom;
|
||||
/* IO */
|
||||
uint8_t write_data;
|
||||
uint8_t write_a;
|
||||
uint8_t write_d;
|
||||
uint8_t write_a_en;
|
||||
uint8_t write_d_en;
|
||||
uint8_t write_fm_address;
|
||||
uint8_t write_fm_data;
|
||||
uint8_t write_mode_address;
|
||||
uint8_t address;
|
||||
uint8_t data;
|
||||
/* Envelope generator */
|
||||
uint8_t eg_counter_state;
|
||||
uint8_t eg_counter_state_prev;
|
||||
uint32_t eg_timer;
|
||||
uint8_t eg_timer_low_lock;
|
||||
uint8_t eg_timer_carry;
|
||||
uint8_t eg_timer_shift;
|
||||
uint8_t eg_timer_shift_lock;
|
||||
uint8_t eg_timer_shift_stop;
|
||||
uint8_t eg_state[18];
|
||||
uint8_t eg_level[18];
|
||||
uint8_t eg_kon;
|
||||
uint32_t eg_dokon;
|
||||
uint8_t eg_off;
|
||||
uint8_t eg_rate;
|
||||
uint8_t eg_maxrate;
|
||||
uint8_t eg_zerorate;
|
||||
uint8_t eg_inc_lo;
|
||||
uint8_t eg_inc_hi;
|
||||
uint8_t eg_rate_hi;
|
||||
uint16_t eg_sl;
|
||||
uint16_t eg_ksltl;
|
||||
uint8_t eg_out;
|
||||
uint8_t eg_silent;
|
||||
/* Phase generator */
|
||||
uint16_t pg_fnum;
|
||||
uint8_t pg_block;
|
||||
uint16_t pg_out;
|
||||
uint32_t pg_inc;
|
||||
uint32_t pg_phase[18];
|
||||
uint32_t pg_phase_next;
|
||||
/* Operator */
|
||||
int16_t op_fb1[9];
|
||||
int16_t op_fb2[9];
|
||||
int16_t op_fbsum;
|
||||
int16_t op_mod;
|
||||
uint8_t op_neg;
|
||||
uint16_t op_logsin;
|
||||
uint16_t op_exp_m;
|
||||
uint16_t op_exp_s;
|
||||
/* Channel */
|
||||
int16_t ch_out;
|
||||
int16_t ch_out_hh;
|
||||
int16_t ch_out_tm;
|
||||
int16_t ch_out_bd;
|
||||
int16_t ch_out_sd;
|
||||
int16_t ch_out_tc;
|
||||
/* LFO */
|
||||
uint16_t lfo_counter;
|
||||
uint8_t lfo_vib_counter;
|
||||
uint16_t lfo_am_counter;
|
||||
uint8_t lfo_am_step;
|
||||
uint8_t lfo_am_dir;
|
||||
uint8_t lfo_am_car;
|
||||
uint8_t lfo_am_out;
|
||||
/* Register set */
|
||||
uint16_t fnum[9];
|
||||
uint8_t block[9];
|
||||
uint8_t kon[9];
|
||||
uint8_t son[9];
|
||||
uint8_t vol[9];
|
||||
uint8_t inst[9];
|
||||
uint8_t rhythm;
|
||||
uint8_t testmode;
|
||||
opll_patch_t patch;
|
||||
uint8_t c_instr;
|
||||
uint8_t c_op;
|
||||
uint8_t c_tl;
|
||||
uint8_t c_dc;
|
||||
uint8_t c_dm;
|
||||
uint8_t c_fb;
|
||||
uint8_t c_am;
|
||||
uint8_t c_vib;
|
||||
uint8_t c_et;
|
||||
uint8_t c_ksr;
|
||||
uint8_t c_ksr_freq;
|
||||
uint8_t c_ksl_freq;
|
||||
uint8_t c_ksl_block;
|
||||
uint8_t c_multi;
|
||||
uint8_t c_ksl;
|
||||
uint8_t c_adrr[3];
|
||||
uint8_t c_sl;
|
||||
uint16_t c_fnum;
|
||||
uint16_t c_block;
|
||||
/* Rhythm mode */
|
||||
int8_t rm_enable;
|
||||
uint32_t rm_noise;
|
||||
uint32_t rm_select;
|
||||
uint8_t rm_hh_bit2;
|
||||
uint8_t rm_hh_bit3;
|
||||
uint8_t rm_hh_bit7;
|
||||
uint8_t rm_hh_bit8;
|
||||
uint8_t rm_tc_bit3;
|
||||
uint8_t rm_tc_bit5;
|
||||
|
||||
int16_t output_m;
|
||||
int16_t output_r;
|
||||
|
||||
} opll_t;
|
||||
|
||||
void OPLL_Reset(opll_t *chip, uint32_t chip_type);
|
||||
void OPLL_Clock(opll_t *chip, int32_t *buffer);
|
||||
void OPLL_Write(opll_t *chip, uint32_t port, uint8_t data);
|
||||
#endif
|
||||
+128
-13
@@ -3,7 +3,7 @@
|
||||
* Sound Hardware
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2018 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -44,7 +44,7 @@
|
||||
#define YM2612_CLOCK_RATIO (7*6)
|
||||
|
||||
/* FM output buffer (large enough to hold a whole frame at original chips rate) */
|
||||
#ifdef HAVE_YM3438_CORE
|
||||
#if defined(HAVE_YM3438_CORE) || defined(HAVE_OPLL_CORE)
|
||||
static int fm_buffer[1080 * 2 * 24];
|
||||
#else
|
||||
static int fm_buffer[1080 * 2];
|
||||
@@ -72,6 +72,14 @@ static int ym3438_sample[2];
|
||||
static int ym3438_cycles;
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_OPLL_CORE
|
||||
static opll_t opll;
|
||||
static int opll_accm[18][2];
|
||||
static int opll_sample;
|
||||
static int opll_cycles;
|
||||
static int opll_status;
|
||||
#endif
|
||||
|
||||
/* Run FM chip until required M-cycles */
|
||||
INLINE void fm_update(int cycles)
|
||||
{
|
||||
@@ -126,7 +134,7 @@ static unsigned int YM2612_Read(unsigned int cycles, unsigned int a)
|
||||
if ((a == 0) || (config.ym2612 > YM2612_DISCRETE))
|
||||
{
|
||||
/* synchronize FM chip with CPU */
|
||||
fm_update(cycles - fm_cycles_ratio + 1);
|
||||
fm_update(cycles);
|
||||
|
||||
/* read FM status */
|
||||
if (cycles >= fm_cycles_busy)
|
||||
@@ -167,6 +175,11 @@ static void YM2413_Write(unsigned int cycles, unsigned int a, unsigned int v)
|
||||
YM2413Write(a, v);
|
||||
}
|
||||
|
||||
static unsigned int YM2413_Read(unsigned int cycles, unsigned int a)
|
||||
{
|
||||
return YM2413Read();
|
||||
}
|
||||
|
||||
#ifdef HAVE_YM3438_CORE
|
||||
static void YM3438_Update(int *buffer, int length)
|
||||
{
|
||||
@@ -211,13 +224,66 @@ static void YM3438_Write(unsigned int cycles, unsigned int a, unsigned int v)
|
||||
static unsigned int YM3438_Read(unsigned int cycles, unsigned int a)
|
||||
{
|
||||
/* synchronize FM chip with CPU */
|
||||
fm_update(cycles - fm_cycles_ratio + 1);
|
||||
fm_update(cycles);
|
||||
|
||||
/* read FM status */
|
||||
return OPN2_Read(&ym3438, a);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_OPLL_CORE
|
||||
static void OPLL2413_Update(int* buffer, int length)
|
||||
{
|
||||
int i, j;
|
||||
for (i = 0; i < length; i++)
|
||||
{
|
||||
OPLL_Clock(&opll, opll_accm[opll_cycles]);
|
||||
opll_cycles = (opll_cycles + 1) % 18;
|
||||
if (opll_cycles == 0)
|
||||
{
|
||||
opll_sample = 0;
|
||||
for (j = 0; j < 18; j++)
|
||||
{
|
||||
opll_sample += opll_accm[j][0] + opll_accm[j][1];
|
||||
}
|
||||
}
|
||||
*buffer++ = opll_sample * 16 * opll_status;
|
||||
*buffer++ = opll_sample * 16 * opll_status;
|
||||
}
|
||||
}
|
||||
|
||||
static void OPLL2413_Reset(unsigned int cycles)
|
||||
{
|
||||
/* synchronize FM chip with CPU */
|
||||
fm_update(cycles);
|
||||
|
||||
/* reset FM chip */
|
||||
OPLL_Reset(&opll, opll_type_ym2413);
|
||||
}
|
||||
|
||||
static void OPLL2413_Write(unsigned int cycles, unsigned int a, unsigned int v)
|
||||
{
|
||||
if (!(a&2))
|
||||
{
|
||||
/* synchronize FM chip with CPU */
|
||||
fm_update(cycles);
|
||||
|
||||
/* write FM register */
|
||||
OPLL_Write(&opll, a, v);
|
||||
}
|
||||
else
|
||||
{
|
||||
opll_status = v&1;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int OPLL2413_Read(unsigned int cycles, unsigned int a)
|
||||
{
|
||||
return 0xf8 | opll_status;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void sound_init( void )
|
||||
{
|
||||
/* Initialize FM chip */
|
||||
@@ -257,14 +323,34 @@ void sound_init( void )
|
||||
else
|
||||
{
|
||||
/* YM2413 */
|
||||
YM2413Init();
|
||||
YM_Update = (config.ym2413 & 1) ? YM2413Update : NULL;
|
||||
fm_reset = YM2413_Reset;
|
||||
fm_write = YM2413_Write;
|
||||
fm_read = NULL;
|
||||
#ifdef HAVE_OPLL_CORE
|
||||
if (config.opll)
|
||||
{
|
||||
/* Nuked OPLL */
|
||||
memset(&opll, 0, sizeof(opll));
|
||||
memset(&opll_accm, 0, sizeof(opll_accm));
|
||||
opll_sample = 0;
|
||||
opll_status = 0;
|
||||
YM_Update = (config.ym2413 & 1) ? OPLL2413_Update : NULL;
|
||||
fm_reset = OPLL2413_Reset;
|
||||
fm_write = OPLL2413_Write;
|
||||
fm_read = OPLL2413_Read;
|
||||
|
||||
/* chip is running at ZCLK / 72 = MCLK / 15 / 72 */
|
||||
fm_cycles_ratio = 72 * 15;
|
||||
/* chip is running at internal clock */
|
||||
fm_cycles_ratio = 4 * 15;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
YM2413Init();
|
||||
YM_Update = (config.ym2413 & 1) ? YM2413Update : NULL;
|
||||
fm_reset = YM2413_Reset;
|
||||
fm_write = YM2413_Write;
|
||||
fm_read = YM2413_Read;
|
||||
|
||||
/* chip is running at ZCLK / 72 = MCLK / 15 / 72 */
|
||||
fm_cycles_ratio = 72 * 15;
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize PSG chip */
|
||||
@@ -401,7 +487,21 @@ int sound_context_save(uint8 *state)
|
||||
}
|
||||
else
|
||||
{
|
||||
save_param(YM2413GetContextPtr(),YM2413GetContextSize());
|
||||
#ifdef HAVE_OPLL_CORE
|
||||
save_param(&config.opll, sizeof(config.opll));
|
||||
if (config.opll)
|
||||
{
|
||||
save_param(&opll, sizeof(opll));
|
||||
save_param(&opll_accm, sizeof(opll_accm));
|
||||
save_param(&opll_sample, sizeof(opll_sample));
|
||||
save_param(&opll_cycles, sizeof(opll_cycles));
|
||||
save_param(&opll_status, sizeof(opll_status));
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
save_param(YM2413GetContextPtr(),YM2413GetContextSize());
|
||||
}
|
||||
}
|
||||
|
||||
bufferptr += psg_context_save(&state[bufferptr]);
|
||||
@@ -437,7 +537,22 @@ int sound_context_load(uint8 *state)
|
||||
}
|
||||
else
|
||||
{
|
||||
load_param(YM2413GetContextPtr(),YM2413GetContextSize());
|
||||
#ifdef HAVE_OPLL_CORE
|
||||
uint8 config_opll;
|
||||
load_param(&config_opll, sizeof(config_opll));
|
||||
if (config_opll)
|
||||
{
|
||||
load_param(&opll, sizeof(opll));
|
||||
load_param(&opll_accm, sizeof(opll_accm));
|
||||
load_param(&opll_sample, sizeof(opll_sample));
|
||||
load_param(&opll_cycles, sizeof(opll_cycles));
|
||||
load_param(&opll_status, sizeof(opll_status));
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
load_param(YM2413GetContextPtr(),YM2413GetContextSize());
|
||||
}
|
||||
}
|
||||
|
||||
bufferptr += psg_context_load(&state[bufferptr]);
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* Sound Hardware
|
||||
*
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2018 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2007-2020 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
||||
+241
-133
@@ -25,7 +25,21 @@ to do:
|
||||
|
||||
*/
|
||||
|
||||
/** EkeEke (2011): removed multiple chips support, cleaned code & added FM board interface for Genesis Plus GX **/
|
||||
/************************************************/
|
||||
/** Modifications for Genesis Plus GX (EkeEke) **/
|
||||
/************************************************/
|
||||
/** 2011/xx/xx: removed multiple chips support, cleaned code & added FM board interface **/
|
||||
/** 2021/04/23: fixed synchronization of carrier/modulator phase reset after channel Key ON (fixes Japanese Master System BIOS music) **/
|
||||
/** 2021/04/24: fixed intruments ROM (verified on YM2413B die, cf. https://siliconpr0n.org/archive/doku.php?id=vendor:yamaha:opl2#ym2413_instrument_rom) **/
|
||||
/** 2021/04/24: fixed EG resolution bits (verified on YM2413B die, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-03-20) **/
|
||||
/** 2021/04/24: fixed EG dump rate (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-12-31) **/
|
||||
/** 2021/04/25: fixed EG behavior for fastest attack rates (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2017-01-26) **/
|
||||
/** 2021/04/25: fixed EG behavior when SL = 0 (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-12-24) **/
|
||||
/** 2021/04/25: improved EG sustain phase transition comparator accuracy (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-12-31) **/
|
||||
/** 2021/05/04: improved EG increment steps accuracy (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-03-20) **/
|
||||
/** 2021/05/08: improved EG transitions accuracy (verified against https://github.com/nukeykt/Nuked-OPLL/blob/master/opll.c) **/
|
||||
/** 2021/05/11: improved EG attack phase algorithm accuracy (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2017-01-26) **/
|
||||
/************************************************/
|
||||
|
||||
#include "shared.h"
|
||||
|
||||
@@ -40,7 +54,7 @@ to do:
|
||||
#define ENV_LEN (1<<ENV_BITS)
|
||||
#define ENV_STEP (128.0/ENV_LEN)
|
||||
|
||||
#define MAX_ATT_INDEX ((1<<(ENV_BITS-2))-1) /*255*/
|
||||
#define MAX_ATT_INDEX ((1<<(ENV_BITS-3))-1) /*127*/
|
||||
#define MIN_ATT_INDEX (0)
|
||||
|
||||
/* sinwave entries */
|
||||
@@ -219,67 +233,100 @@ static const UINT32 sl_tab[16]={
|
||||
#undef SC
|
||||
|
||||
|
||||
#define RATE_STEPS (8)
|
||||
static const unsigned char eg_inc[15*RATE_STEPS]={
|
||||
#define RATE_STEPS (16)
|
||||
|
||||
/*cycle:0 1 2 3 4 5 6 7*/
|
||||
static const unsigned char eg_inc[14*RATE_STEPS]={
|
||||
|
||||
/* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
|
||||
/* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
|
||||
/* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
|
||||
/* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
|
||||
/*cycle:0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15*/
|
||||
|
||||
/* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
|
||||
/* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
|
||||
/* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
|
||||
/* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
|
||||
/* 0 */ 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, /* infinity rates for decay(s) */
|
||||
|
||||
/* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
|
||||
/* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
|
||||
/*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
|
||||
/*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
|
||||
/* 1 */ 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, /* rates 01..12 0 for decay(s) (increment by 0 or 1) */
|
||||
/* 2 */ 0,1, 1,1, 0,1, 0,1, 0,1, 1,1, 0,1, 0,1, /* rates 01..12 1 for decay(s) */
|
||||
/* 3 */ 0,1, 1,1, 0,1, 1,1, 0,1, 1,1, 0,1, 1,1, /* rates 01..12 2 for decay(s) */
|
||||
/* 4 */ 0,1, 1,1, 1,1, 1,1, 0,1, 1,1, 1,1, 1,1, /* rates 01..12 3 for decay(s) */
|
||||
|
||||
/* 5 */ 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, /* rate 13 0 for decay(s) (increment by 0 or 1) */
|
||||
/* 6 */ 0,1, 0,1, 1,1, 1,1, 0,1, 0,1, 0,1, 0,1, /* rate 13 1 for decay(s) */
|
||||
/* 7 */ 0,1, 0,1, 1,1, 1,1, 0,1, 0,1, 1,1, 1,1, /* rate 13 2 for decay(s) */
|
||||
/* 8 */ 0,1, 0,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, /* rate 13 3 for decay(s) */
|
||||
|
||||
/* 9 */ 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, /* rate 14 0 for decay(s) (increment by 1) */
|
||||
/*10 */ 1,1, 1,1, 2,2, 2,2, 1,1, 1,1, 1,1, 1,1, /* rate 14 1 for decay(s) */
|
||||
/*11 */ 1,1, 1,1, 2,2, 2,2, 1,1, 1,1, 2,2, 2,2, /* rate 14 2 for decay(s) */
|
||||
/*12 */ 1,1, 1,1, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, /* rate 14 3 for decay(s) */
|
||||
|
||||
/*13 */ 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, /* rates 15 0, 15 1, 15 2, 15 3 for decay(s) (increment by 2) */
|
||||
|
||||
/*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 4) */
|
||||
/*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 2, 15 3 for attack */
|
||||
/*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
|
||||
};
|
||||
|
||||
static const unsigned char eg_mul[17*RATE_STEPS]={
|
||||
|
||||
/*cycle:0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15*/
|
||||
|
||||
/* 0 */ 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack */
|
||||
|
||||
/* 1 */ 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, /* rates 01..11 0 for attack */
|
||||
/* 2 */ 0,1, 1,1, 0,1, 0,1, 0,1, 1,1, 0,1, 0,1, /* rates 01..11 1 for attack */
|
||||
/* 3 */ 0,1, 1,1, 0,1, 1,1, 0,1, 1,1, 0,1, 1,1, /* rates 01..11 2 for attack */
|
||||
/* 4 */ 0,1, 1,1, 1,1, 1,1, 0,1, 1,1, 1,1, 1,1, /* rates 01..11 3 for attack */
|
||||
|
||||
/* 5 */ 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, /* rate 12 0 for attack */
|
||||
/* 6 */ 1,1, 1,1, 2,2, 2,2, 1,1, 1,1, 1,1, 1,1, /* rate 12 1 for attack */
|
||||
/* 7 */ 1,1, 1,1, 2,2, 2,2, 1,1, 1,1, 2,2, 2,2, /* rate 12 2 for attack */
|
||||
/* 8 */ 1,1, 1,1, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, /* rate 12 3 for attack */
|
||||
|
||||
/* 9 */ 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, /* rate 13 0 for attack */
|
||||
/*10 */ 2,2, 2,2, 4,4, 4,4, 2,2, 2,2, 2,2, 2,2, /* rate 13 1 for attack */
|
||||
/*11 */ 2,2, 2,2, 4,4, 4,4, 2,2, 2,2, 4,4, 4,4, /* rate 13 2 for attack */
|
||||
/*12 */ 2,2, 2,2, 4,4, 4,4, 4,4, 4,4, 4,4, 4,4, /* rate 13 3 for attack */
|
||||
|
||||
/*13 */ 4,4, 4,4, 4,4, 4,4, 4,4, 4,4, 4,4, 4,4, /* rate 14 0 for attack */
|
||||
/*14 */ 4,4, 4,4, 8,8, 8,8, 4,4, 4,4, 4,4, 4,4, /* rate 14 1 for attack */
|
||||
/*15 */ 4,4, 4,4, 8,8, 8,8, 4,4, 4,4, 8,8, 8,8, /* rate 14 2 for attack */
|
||||
/*16 */ 4,4, 4,4, 8,8, 8,8, 8,8, 8,8, 8,8, 8,8, /* rate 14 3 for attack */
|
||||
|
||||
};
|
||||
|
||||
#define O(a) (a*RATE_STEPS)
|
||||
|
||||
/*note that there is no O(13) in this table - it's directly in the code */
|
||||
static const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
|
||||
|
||||
/* 16 infinite time rates */
|
||||
O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
|
||||
O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
|
||||
O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
|
||||
O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
|
||||
|
||||
/* rates 00-12 */
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
O( 0),O( 1),O( 2),O( 3),
|
||||
/* rate 00 */
|
||||
O( 0),O( 0),O( 0),O( 0), /* never used since infinite time rates are directly forced in the code for rate 00 */
|
||||
|
||||
/* rate 13 */
|
||||
O( 4),O( 5),O( 6),O( 7),
|
||||
/* rates 01-11 */
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
|
||||
/* rate 14 */
|
||||
O( 8),O( 9),O(10),O(11),
|
||||
/* rate 12 */ /* only used for decay(s), handled directly in the code for attack */
|
||||
O( 1),O( 2),O( 3),O( 4),
|
||||
|
||||
/* rate 15 */
|
||||
O(12),O(12),O(12),O(12),
|
||||
/* rate 13 */ /* only used for decay(s), handled directly in the code for attack */
|
||||
O( 5),O( 6),O( 7),O( 8),
|
||||
|
||||
/* rate 14 */ /* only used for decay(s), handled directly in the code for attack */
|
||||
O( 9),O(10),O(11),O(12),
|
||||
|
||||
/* rate 15 */ /* only used for decay(s), handled directly in the code for attack */
|
||||
O(13),O(13),O(13),O(13),
|
||||
|
||||
/* 16 dummy rates (same as 15 3) */
|
||||
O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
|
||||
O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
|
||||
O(13),O(13),O(13),O(13),O(13),O(13),O(13),O(13),
|
||||
O(13),O(13),O(13),O(13),O(13),O(13),O(13),O(13),
|
||||
|
||||
};
|
||||
#undef O
|
||||
@@ -287,15 +334,19 @@ O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
|
||||
/*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
|
||||
/*shift 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0 */
|
||||
/*mask 8191, 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0 */
|
||||
/*NB: for attack, above mask values lower 2 bits are cleared and rate 12 shift value is equal to 0 */
|
||||
|
||||
#define O(a) (a*1)
|
||||
static const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
|
||||
/* 16 infinite time rates */
|
||||
O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
|
||||
O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
|
||||
|
||||
/* rates 00-12 */
|
||||
O(13),O(13),O(13),O(13),
|
||||
/* 16 infinite time rates */
|
||||
O(13),O(13),O(13),O(13),O(13),O(13),O(13),O(13),
|
||||
O(13),O(13),O(13),O(13),O(13),O(13),O(13),O(13),
|
||||
|
||||
/* rate 00 */
|
||||
O(13),O(13),O(13),O(13), /* never used since infinite time rates are directly forced in the code for rate 00 */
|
||||
|
||||
/* rates 01-11 */
|
||||
O(12),O(12),O(12),O(12),
|
||||
O(11),O(11),O(11),O(11),
|
||||
O(10),O(10),O(10),O(10),
|
||||
@@ -307,15 +358,17 @@ O( 5),O( 5),O( 5),O( 5),
|
||||
O( 4),O( 4),O( 4),O( 4),
|
||||
O( 3),O( 3),O( 3),O( 3),
|
||||
O( 2),O( 2),O( 2),O( 2),
|
||||
|
||||
/* rate 12 */ /* only used for decay(s), handled directly in the code for attack */
|
||||
O( 1),O( 1),O( 1),O( 1),
|
||||
|
||||
/* rate 13 */
|
||||
/* rate 13 */ /* only used for decay(s), handled directly in the code for attack */
|
||||
O( 0),O( 0),O( 0),O( 0),
|
||||
|
||||
/* rate 14 */
|
||||
/* rate 14 */ /* only used for decay(s), handled directly in the code for attack */
|
||||
O( 0),O( 0),O( 0),O( 0),
|
||||
|
||||
/* rate 15 */
|
||||
/* rate 15 */ /* only used for decay(s), handled directly in the code for attack */
|
||||
O( 0),O( 0),O( 0),O( 0),
|
||||
|
||||
/* 16 dummy rates (same as 15 3) */
|
||||
@@ -455,45 +508,71 @@ static const INT8 lfo_pm_table[8*8] = {
|
||||
- LFO PM and AM enable are 100% correct
|
||||
- waveform DC and DM select are 100% correct
|
||||
*/
|
||||
/* 2021/04/23: corrected with values extracted from YM2413 instrument ROM, cf. https://siliconpr0n.org/archive/doku.php?id=vendor:yamaha:opl2#ym2413_instrument_rom */
|
||||
|
||||
static unsigned char table[19][8] = {
|
||||
/* MULT MULT modTL DcDmFb AR/DR AR/DR SL/RR SL/RR */
|
||||
/* 0 1 2 3 4 5 6 7 */
|
||||
{0x49, 0x4c, 0x4c, 0x12, 0x00, 0x00, 0x00, 0x00 }, /* 0 */
|
||||
/*{0x49, 0x4c, 0x4c, 0x12, 0x00, 0x00, 0x00, 0x00 }, */ /* 0 */
|
||||
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* 0 */
|
||||
|
||||
{0x61, 0x61, 0x1e, 0x17, 0xf0, 0x78, 0x00, 0x17 }, /* 1 */
|
||||
{0x13, 0x41, 0x1e, 0x0d, 0xd7, 0xf7, 0x13, 0x13 }, /* 2 */
|
||||
{0x13, 0x01, 0x99, 0x04, 0xf2, 0xf4, 0x11, 0x23 }, /* 3 */
|
||||
{0x21, 0x61, 0x1b, 0x07, 0xaf, 0x64, 0x40, 0x27 }, /* 4 */
|
||||
/*{0x61, 0x61, 0x1e, 0x17, 0xf0, 0x78, 0x00, 0x17 }, */ /* 1 */
|
||||
{0x71, 0x61, 0x1e, 0x17, 0xd0, 0x78, 0x00, 0x17 }, /* 1 */
|
||||
|
||||
/*{0x13, 0x41, 0x1e, 0x0d, 0xd7, 0xf7, 0x13, 0x13 }, */ /* 2 */
|
||||
{0x13, 0x41, 0x1a, 0x0d, 0xd8, 0xf7, 0x23, 0x13 }, /* 2 */
|
||||
|
||||
/*{0x13, 0x01, 0x99, 0x04, 0xf2, 0xf4, 0x11, 0x23 }, */ /* 3 */
|
||||
{0x13, 0x01, 0x99, 0x00, 0xf2, 0xc4, 0x11, 0x23 }, /* 3 */
|
||||
|
||||
/*{0x21, 0x61, 0x1b, 0x07, 0xaf, 0x64, 0x40, 0x27 }, */ /* 4 */
|
||||
{0x31, 0x61, 0x0e, 0x07, 0xa8, 0x64, 0x70, 0x27 }, /* 4 */
|
||||
|
||||
/*{0x22, 0x21, 0x1e, 0x09, 0xf0, 0x76, 0x08, 0x28 }, */ /* 5 */
|
||||
{0x22, 0x21, 0x1e, 0x06, 0xf0, 0x75, 0x08, 0x18 }, /* 5 */
|
||||
/*{0x22, 0x21, 0x1e, 0x06, 0xf0, 0x75, 0x08, 0x18 }, */ /* 5 */
|
||||
{0x32, 0x21, 0x1e, 0x06, 0xe0, 0x76, 0x00, 0x28 }, /* 5 */
|
||||
|
||||
/*{0x31, 0x22, 0x16, 0x09, 0x90, 0x7f, 0x00, 0x08 }, */ /* 6 */
|
||||
{0x31, 0x22, 0x16, 0x05, 0x90, 0x71, 0x00, 0x13 }, /* 6 */
|
||||
/*{0x31, 0x22, 0x16, 0x05, 0x90, 0x71, 0x00, 0x13 }, */ /* 6 */
|
||||
{0x31, 0x22, 0x16, 0x05, 0xe0, 0x71, 0x00, 0x18 }, /* 6 */
|
||||
|
||||
{0x21, 0x61, 0x1d, 0x07, 0x82, 0x80, 0x10, 0x17 }, /* 7 */
|
||||
{0x23, 0x21, 0x2d, 0x16, 0xc0, 0x70, 0x07, 0x07 }, /* 8 */
|
||||
{0x61, 0x61, 0x1b, 0x06, 0x64, 0x65, 0x10, 0x17 }, /* 9 */
|
||||
/*{0x21, 0x61, 0x1d, 0x07, 0x82, 0x80, 0x10, 0x17 }, */ /* 7 */
|
||||
{0x21, 0x61, 0x1d, 0x07, 0x82, 0x81, 0x10, 0x07 }, /* 7 */
|
||||
|
||||
/* {0x61, 0x61, 0x0c, 0x08, 0x85, 0xa0, 0x79, 0x07 }, */ /* A */
|
||||
{0x61, 0x61, 0x0c, 0x18, 0x85, 0xf0, 0x70, 0x07 }, /* A */
|
||||
/*{0x23, 0x21, 0x2d, 0x16, 0xc0, 0x70, 0x07, 0x07 }, */ /* 8 */
|
||||
{0x23, 0x21, 0x2d, 0x14, 0xa2, 0x72, 0x00, 0x07 }, /* 8 */
|
||||
|
||||
{0x23, 0x01, 0x07, 0x11, 0xf0, 0xa4, 0x00, 0x22 }, /* B */
|
||||
{0x97, 0xc1, 0x24, 0x07, 0xff, 0xf8, 0x22, 0x12 }, /* C */
|
||||
{0x61, 0x61, 0x1b, 0x06, 0x64, 0x65, 0x10, 0x17 }, /* 9 */
|
||||
|
||||
/* {0x61, 0x10, 0x0c, 0x08, 0xf2, 0xc4, 0x40, 0xc8 }, */ /* D */
|
||||
{0x61, 0x10, 0x0c, 0x05, 0xf2, 0xf4, 0x40, 0x44 }, /* D */
|
||||
/*{0x61, 0x61, 0x0c, 0x08, 0x85, 0xa0, 0x79, 0x07 }, */ /* A */
|
||||
/*{0x61, 0x61, 0x0c, 0x18, 0x85, 0xf0, 0x70, 0x07 }, */ /* A */
|
||||
{0x41, 0x61, 0x0b, 0x18, 0x85, 0xf7, 0x71, 0x07 }, /* A */
|
||||
|
||||
{0x01, 0x01, 0x55, 0x03, 0xf3, 0x92, 0xf3, 0xf3 }, /* E */
|
||||
{0x61, 0x41, 0x89, 0x03, 0xf1, 0xf4, 0xf0, 0x13 }, /* F */
|
||||
/*{0x23, 0x01, 0x07, 0x11, 0xf0, 0xa4, 0x00, 0x22 }, */ /* B */
|
||||
{0x13, 0x01, 0x83, 0x11, 0xfa, 0xe4, 0x10, 0x04 }, /* B */
|
||||
|
||||
/*{0x97, 0xc1, 0x24, 0x07, 0xff, 0xf8, 0x22, 0x12 }, */ /* C */
|
||||
{0x17, 0xc1, 0x24, 0x07, 0xf8, 0xf8, 0x22, 0x12 }, /* C */
|
||||
|
||||
/*{0x61, 0x10, 0x0c, 0x08, 0xf2, 0xc4, 0x40, 0xc8 }, */ /* D */
|
||||
/*{0x61, 0x10, 0x0c, 0x05, 0xf2, 0xf4, 0x40, 0x44 }, */ /* D */
|
||||
{0x61, 0x50, 0x0c, 0x05, 0xc2, 0xf5, 0x20, 0x42 }, /* D */
|
||||
|
||||
/*{0x01, 0x01, 0x55, 0x03, 0xf3, 0x92, 0xf3, 0xf3 }, */ /* E */
|
||||
{0x01, 0x01, 0x55, 0x03, 0xc9, 0x95, 0x03, 0x02 }, /* E */
|
||||
|
||||
/*{0x61, 0x41, 0x89, 0x03, 0xf1, 0xf4, 0xf0, 0x13 }, */ /* F */
|
||||
{0x61, 0x41, 0x89, 0x03, 0xf1, 0xe4, 0x40, 0x13 }, /* F */
|
||||
|
||||
/* drum instruments definitions */
|
||||
/* MULTI MULTI modTL xxx AR/DR AR/DR SL/RR SL/RR */
|
||||
/* 0 1 2 3 4 5 6 7 */
|
||||
{0x01, 0x01, 0x16, 0x00, 0xfd, 0xf8, 0x2f, 0x6d },/* BD(multi verified, modTL verified, mod env - verified(close), carr. env verifed) */
|
||||
{0x01, 0x01, 0x00, 0x00, 0xd8, 0xd8, 0xf9, 0xf8 },/* HH(multi verified), SD(multi not used) */
|
||||
{0x05, 0x01, 0x00, 0x00, 0xf8, 0xba, 0x49, 0x55 },/* TOM(multi,env verified), TOP CYM(multi verified, env verified) */
|
||||
/*{0x01, 0x01, 0x16, 0x00, 0xfd, 0xf8, 0x2f, 0x6d },*/ /* BD(multi verified, modTL verified, mod env - verified(close), carr. env verifed) */
|
||||
/*{0x01, 0x01, 0x00, 0x00, 0xd8, 0xd8, 0xf9, 0xf8 },*/ /* HH(multi verified), SD(multi not used) */
|
||||
/*{0x05, 0x01, 0x00, 0x00, 0xf8, 0xba, 0x49, 0x55 },*/ /* TOM(multi,env verified), TOP CYM(multi verified, env verified) */
|
||||
{0x01, 0x01, 0x18, 0x0f, 0xdf, 0xf8, 0x6a, 0x6d }, /* BD */
|
||||
{0x01, 0x01, 0x00, 0x00, 0xc8, 0xd8, 0xa7, 0x48 }, /* HH, SD */
|
||||
{0x05, 0x01, 0x00, 0x00, 0xf8, 0xaa, 0x59, 0x55 } /* TOM, TOP CYM */
|
||||
};
|
||||
|
||||
static signed int output[2];
|
||||
@@ -542,47 +621,55 @@ INLINE void advance(void)
|
||||
|
||||
switch(op->state)
|
||||
{
|
||||
case EG_DMP: /* dump phase */
|
||||
/*dump phase is performed by both operators in each channel*/
|
||||
/*when CARRIER envelope gets down to zero level,
|
||||
** phases in BOTH opearators are reset (at the same time ?)
|
||||
*/
|
||||
if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_dp)-1) ) )
|
||||
case EG_DMP: /* dump phase */
|
||||
if ( (op->volume & ~3) == (MAX_ATT_INDEX & ~3) ) /* envelope level lowest 2 bits are ignored by the comparator */
|
||||
{
|
||||
op->volume += eg_inc[op->eg_sel_dp + ((ym2413.eg_cnt>>op->eg_sh_dp)&7)];
|
||||
op->state = EG_ATT;
|
||||
|
||||
if ( op->volume >= MAX_ATT_INDEX )
|
||||
/* force envelope to zero when attack rate is set to 15.0-15.3 */
|
||||
if ((op->ar + op->ksr) >= 16+60)
|
||||
{
|
||||
op->volume = MAX_ATT_INDEX;
|
||||
op->state = EG_ATT;
|
||||
/* restart Phase Generator */
|
||||
op->phase = 0;
|
||||
op->volume = MIN_ATT_INDEX;
|
||||
}
|
||||
|
||||
/*dump phase is performed by both operators in each channel*/
|
||||
/*when CARRIER envelope gets down to zero level,
|
||||
*phases in BOTH operators are reset (at the same time ?)
|
||||
*/
|
||||
if (i&1)
|
||||
{
|
||||
CH->SLOT[0].phase = CH->SLOT[1].phase = 0;
|
||||
}
|
||||
}
|
||||
else if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_dp)-1) ) )
|
||||
{
|
||||
op->volume += eg_inc[op->eg_sel_dp + ((ym2413.eg_cnt>>op->eg_sh_dp)&15)];
|
||||
}
|
||||
break;
|
||||
|
||||
case EG_ATT: /* attack phase */
|
||||
if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
|
||||
case EG_ATT: /* attack phase */
|
||||
if (op->volume == MIN_ATT_INDEX)
|
||||
{
|
||||
op->volume += (~op->volume *
|
||||
(eg_inc[op->eg_sel_ar + ((ym2413.eg_cnt>>op->eg_sh_ar)&7)])
|
||||
) >>2;
|
||||
|
||||
if (op->volume <= MIN_ATT_INDEX)
|
||||
{
|
||||
op->volume = MIN_ATT_INDEX;
|
||||
op->state = EG_DEC;
|
||||
}
|
||||
op->state = EG_DEC;
|
||||
}
|
||||
else if ( !(ym2413.eg_cnt & (((1<<op->eg_sh_ar)-1) & ~3)) )
|
||||
{
|
||||
op->volume += (~op->volume * (eg_mul[op->eg_sel_ar + ((ym2413.eg_cnt>>op->eg_sh_ar)&15)]))>>4;
|
||||
}
|
||||
break;
|
||||
|
||||
case EG_DEC: /* decay phase */
|
||||
if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
|
||||
if ( (op->volume & ~7) == op->sl ) /* envelope level lowest 3 bits are ignored by the comparator */
|
||||
{
|
||||
op->volume += eg_inc[op->eg_sel_dr + ((ym2413.eg_cnt>>op->eg_sh_dr)&7)];
|
||||
|
||||
if ( op->volume >= op->sl )
|
||||
op->state = EG_SUS;
|
||||
op->state = EG_SUS;
|
||||
}
|
||||
else if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
|
||||
{
|
||||
op->volume += eg_inc[op->eg_sel_dr + ((ym2413.eg_cnt>>op->eg_sh_dr)&15)];
|
||||
if ( (op->volume & ~3) == (MAX_ATT_INDEX & ~3) ) /* envelope level lowest 2 bits are ignored by the comparator */
|
||||
{
|
||||
op->state = EG_OFF;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -591,19 +678,20 @@ INLINE void advance(void)
|
||||
one can change percusive/non-percussive modes on the fly and
|
||||
the chip will remain in sustain phase - verified on real YM3812 */
|
||||
|
||||
if(op->eg_type) /* non-percussive mode (sustained tone) */
|
||||
if (op->eg_type) /* non-percussive mode (sustained tone) */
|
||||
{
|
||||
/* do nothing */
|
||||
}
|
||||
else /* percussive mode */
|
||||
else /* percussive mode */
|
||||
{
|
||||
/* during sustain phase chip adds Release Rate (in percussive mode) */
|
||||
if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
|
||||
{
|
||||
op->volume += eg_inc[op->eg_sel_rr + ((ym2413.eg_cnt>>op->eg_sh_rr)&7)];
|
||||
|
||||
if ( op->volume >= MAX_ATT_INDEX )
|
||||
op->volume = MAX_ATT_INDEX;
|
||||
op->volume += eg_inc[op->eg_sel_rr + ((ym2413.eg_cnt>>op->eg_sh_rr)&15)];
|
||||
if ( (op->volume & ~3) == (MAX_ATT_INDEX & ~3) ) /* envelope level lowest 2 bits are ignored by the comparator */
|
||||
{
|
||||
op->state = EG_OFF;
|
||||
}
|
||||
}
|
||||
/* else do nothing in sustain phase */
|
||||
}
|
||||
@@ -629,7 +717,7 @@ INLINE void advance(void)
|
||||
*/
|
||||
if ( (i&1) || ((ym2413.rhythm&0x20) && (i>=12)) )/* exclude modulators */
|
||||
{
|
||||
if(op->eg_type) /* non-percussive mode (sustained tone) */
|
||||
if (op->eg_type) /* non-percussive mode (sustained tone) */
|
||||
/*this is correct: use RR when SUS = OFF*/
|
||||
/*and use RS when SUS = ON*/
|
||||
{
|
||||
@@ -637,10 +725,9 @@ INLINE void advance(void)
|
||||
{
|
||||
if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_rs)-1) ) )
|
||||
{
|
||||
op->volume += eg_inc[op->eg_sel_rs + ((ym2413.eg_cnt>>op->eg_sh_rs)&7)];
|
||||
if ( op->volume >= MAX_ATT_INDEX )
|
||||
op->volume += eg_inc[op->eg_sel_rs + ((ym2413.eg_cnt>>op->eg_sh_rs)&15)];
|
||||
if ( (op->volume & ~3) == (MAX_ATT_INDEX & ~3) ) /* envelope level lowest 2 bits are ignored by the comparator */
|
||||
{
|
||||
op->volume = MAX_ATT_INDEX;
|
||||
op->state = EG_OFF;
|
||||
}
|
||||
}
|
||||
@@ -649,23 +736,21 @@ INLINE void advance(void)
|
||||
{
|
||||
if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
|
||||
{
|
||||
op->volume += eg_inc[op->eg_sel_rr + ((ym2413.eg_cnt>>op->eg_sh_rr)&7)];
|
||||
if ( op->volume >= MAX_ATT_INDEX )
|
||||
op->volume += eg_inc[op->eg_sel_rr + ((ym2413.eg_cnt>>op->eg_sh_rr)&15)];
|
||||
if ( (op->volume & ~3) == (MAX_ATT_INDEX & ~3) ) /* envelope level lowest 2 bits are ignored by the comparator */
|
||||
{
|
||||
op->volume = MAX_ATT_INDEX;
|
||||
op->state = EG_OFF;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* percussive mode */
|
||||
else /* percussive mode */
|
||||
{
|
||||
if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_rs)-1) ) )
|
||||
{
|
||||
op->volume += eg_inc[op->eg_sel_rs + ((ym2413.eg_cnt>>op->eg_sh_rs)&7)];
|
||||
if ( op->volume >= MAX_ATT_INDEX )
|
||||
op->volume += eg_inc[op->eg_sel_rs + ((ym2413.eg_cnt>>op->eg_sh_rs)&15)];
|
||||
if ( (op->volume & ~3) == (MAX_ATT_INDEX & ~3) ) /* envelope level lowest 2 bits are ignored by the comparator */
|
||||
{
|
||||
op->volume = MAX_ATT_INDEX;
|
||||
op->state = EG_OFF;
|
||||
}
|
||||
}
|
||||
@@ -673,8 +758,12 @@ INLINE void advance(void)
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
case EG_OFF: /* envelope off */
|
||||
op->volume = MAX_ATT_INDEX;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1142,21 +1231,30 @@ INLINE void CALC_FCSLOT(YM2413_OPLL_CH *CH,YM2413_OPLL_SLOT *SLOT)
|
||||
SLOT->ksr = ksr;
|
||||
|
||||
/* calculate envelope generator rates */
|
||||
if ((SLOT->ar + SLOT->ksr) < 16+62)
|
||||
if ((SLOT->ar + SLOT->ksr) >= 16+60)
|
||||
{
|
||||
SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
|
||||
SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
|
||||
/* attack phase is skipped in case attack rate is set to 15.0-15.3 before attack phase is started */
|
||||
/* during attack phase, in case attack rate is changed to 15.0-15.3, attack phase is blocked */
|
||||
/* (verified on real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2017-01-26) */
|
||||
SLOT->eg_sh_ar = 13;
|
||||
SLOT->eg_sel_ar = 0 * RATE_STEPS;
|
||||
}
|
||||
else
|
||||
else if ((SLOT->ar + SLOT->ksr) >= 16+48)
|
||||
{
|
||||
/* attack rates 12.0 to 14.3 have similar specific behavior */
|
||||
/* (verified on real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2017-01-26) */
|
||||
SLOT->eg_sh_ar = 0;
|
||||
SLOT->eg_sel_ar = 13*RATE_STEPS;
|
||||
SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr] + (4 * RATE_STEPS);
|
||||
}
|
||||
else
|
||||
{
|
||||
SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr];
|
||||
SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr];
|
||||
}
|
||||
SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
|
||||
SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
|
||||
SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
|
||||
SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
|
||||
|
||||
}
|
||||
|
||||
if (CH->sus)
|
||||
@@ -1167,7 +1265,7 @@ INLINE void CALC_FCSLOT(YM2413_OPLL_CH *CH,YM2413_OPLL_SLOT *SLOT)
|
||||
SLOT->eg_sh_rs = eg_rate_shift [SLOT_rs + SLOT->ksr ];
|
||||
SLOT->eg_sel_rs = eg_rate_select[SLOT_rs + SLOT->ksr ];
|
||||
|
||||
SLOT_dp = 16 + (13<<2);
|
||||
SLOT_dp = 16 + (12<<2);
|
||||
SLOT->eg_sh_dp = eg_rate_shift [SLOT_dp + SLOT->ksr ];
|
||||
SLOT->eg_sel_dp = eg_rate_select[SLOT_dp + SLOT->ksr ];
|
||||
}
|
||||
@@ -1225,15 +1323,25 @@ INLINE void set_ar_dr(int slot,int v)
|
||||
|
||||
SLOT->ar = (v>>4) ? 16 + ((v>>4) <<2) : 0;
|
||||
|
||||
if ((SLOT->ar + SLOT->ksr) < 16+62)
|
||||
if ((SLOT->ar + SLOT->ksr) >= 16+60)
|
||||
{
|
||||
SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
|
||||
SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
|
||||
/* attack phase is skipped in case attack rate is set to 15.0-15.3 before attack phase is started */
|
||||
/* during attack phase, in case attack rate is changed to 15.0-15.3, attack phase is blocked */
|
||||
/* (verified on real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2017-01-26) */
|
||||
SLOT->eg_sh_ar = 13;
|
||||
SLOT->eg_sel_ar = 0 * RATE_STEPS;
|
||||
}
|
||||
else
|
||||
else if ((SLOT->ar + SLOT->ksr) >= 16+48)
|
||||
{
|
||||
/* attack rates 12.0 to 14.3 have similar specific behavior */
|
||||
/* (verified on real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2017-01-26) */
|
||||
SLOT->eg_sh_ar = 0;
|
||||
SLOT->eg_sel_ar = 13*RATE_STEPS;
|
||||
SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr] + (4 * RATE_STEPS);
|
||||
}
|
||||
else
|
||||
{
|
||||
SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr];
|
||||
SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr];
|
||||
}
|
||||
|
||||
SLOT->dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
|
||||
|
||||
@@ -20,6 +20,9 @@
|
||||
/*
|
||||
** CHANGELOG:
|
||||
**
|
||||
** 11-05-2021 Eke-Eke (Genesis Plus GX):
|
||||
** - fixed potential issue with SSG-EG inverted attenuation level on Key OFF
|
||||
**
|
||||
** 03-12-2017 Eke-Eke (Genesis Plus GX):
|
||||
** - improved 9-bit DAC emulation accuracy
|
||||
** - added discrete YM2612 DAC distortion emulation ("ladder effect")
|
||||
@@ -684,7 +687,7 @@ INLINE void FM_KEYOFF(FM_CH *CH , int s )
|
||||
{
|
||||
/* convert EG attenuation level */
|
||||
if (SLOT->ssgn ^ (SLOT->ssg&0x04))
|
||||
SLOT->volume = (0x200 - SLOT->volume);
|
||||
SLOT->volume = (0x200 - SLOT->volume) & MAX_ATT_INDEX;
|
||||
|
||||
/* force EG attenuation level */
|
||||
if (SLOT->volume >= 0x200)
|
||||
@@ -749,7 +752,7 @@ INLINE void FM_KEYOFF_CSM(FM_CH *CH , int s )
|
||||
{
|
||||
/* convert EG attenuation level */
|
||||
if (SLOT->ssgn ^ (SLOT->ssg&0x04))
|
||||
SLOT->volume = (0x200 - SLOT->volume);
|
||||
SLOT->volume = (0x200 - SLOT->volume) & MAX_ATT_INDEX;
|
||||
|
||||
/* force EG attenuation level */
|
||||
if (SLOT->volume >= 0x200)
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
#ifdef HAVE_YM3438_CORE
|
||||
/*
|
||||
* Copyright (C) 2017 Alexey Khokholov (Nuke.YKT)
|
||||
* Copyright (C) 2017-2018 Alexey Khokholov (Nuke.YKT)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -40,7 +40,7 @@
|
||||
* OPLx decapsulated(Matthew Gambrell, Olli Niemitalo):
|
||||
* OPL2 ROMs.
|
||||
*
|
||||
* version: 1.0.8
|
||||
* version: 1.0.10
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
@@ -235,7 +235,7 @@ static const Bit32u fm_algorithm[4][6][8] = {
|
||||
|
||||
static Bit32u chip_type = ym3438_mode_readmode;
|
||||
|
||||
void OPN2_DoIO(ym3438_t *chip)
|
||||
static void OPN2_DoIO(ym3438_t *chip)
|
||||
{
|
||||
/* Write signal check */
|
||||
chip->write_a_en = (chip->write_a & 0x03) == 0x01;
|
||||
@@ -249,10 +249,10 @@ void OPN2_DoIO(ym3438_t *chip)
|
||||
chip->write_busy_cnt &= 0x1f;
|
||||
}
|
||||
|
||||
void OPN2_DoRegWrite(ym3438_t *chip)
|
||||
static void OPN2_DoRegWrite(ym3438_t *chip)
|
||||
{
|
||||
Bit32u i;
|
||||
Bit32u slot = chip->slot % 12;
|
||||
Bit32u slot = chip->cycles % 12;
|
||||
Bit32u address;
|
||||
Bit32u channel = chip->channel;
|
||||
/* Update registers */
|
||||
@@ -379,7 +379,7 @@ void OPN2_DoRegWrite(ym3438_t *chip)
|
||||
/* Data */
|
||||
if (chip->write_d_en && (chip->write_data & 0x100) == 0)
|
||||
{
|
||||
switch (chip->address)
|
||||
switch (chip->write_fm_mode_a)
|
||||
{
|
||||
case 0x21: /* LSI test 1 */
|
||||
for (i = 0; i < 8; i++)
|
||||
@@ -458,7 +458,7 @@ void OPN2_DoRegWrite(ym3438_t *chip)
|
||||
/* Address */
|
||||
if (chip->write_a_en)
|
||||
{
|
||||
chip->write_fm_mode_a = chip->write_data & 0xff;
|
||||
chip->write_fm_mode_a = chip->write_data & 0x1ff;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -468,16 +468,18 @@ void OPN2_DoRegWrite(ym3438_t *chip)
|
||||
}
|
||||
}
|
||||
|
||||
void OPN2_PhaseCalcIncrement(ym3438_t *chip)
|
||||
static void OPN2_PhaseCalcIncrement(ym3438_t *chip)
|
||||
{
|
||||
Bit32u chan = chip->channel;
|
||||
Bit32u slot = chip->cycles;
|
||||
Bit32u fnum = chip->pg_fnum;
|
||||
Bit32u fnum_h = fnum >> 4;
|
||||
Bit32u fm;
|
||||
Bit32u basefreq;
|
||||
Bit8u lfo = chip->lfo_pm;
|
||||
Bit8u lfo_l = lfo & 0x0f;
|
||||
Bit8u pms = chip->pms[chip->channel];
|
||||
Bit8u dt = chip->dt[chip->slot];
|
||||
Bit8u pms = chip->pms[chan];
|
||||
Bit8u dt = chip->dt[slot];
|
||||
Bit8u dt_l = dt & 0x03;
|
||||
Bit8u detune = 0;
|
||||
Bit8u block, note;
|
||||
@@ -531,32 +533,32 @@ void OPN2_PhaseCalcIncrement(ym3438_t *chip)
|
||||
basefreq += detune;
|
||||
}
|
||||
basefreq &= 0x1ffff;
|
||||
chip->pg_inc[chip->slot] = (basefreq * chip->multi[chip->slot]) >> 1;
|
||||
chip->pg_inc[chip->slot] &= 0xfffff;
|
||||
chip->pg_inc[slot] = (basefreq * chip->multi[slot]) >> 1;
|
||||
chip->pg_inc[slot] &= 0xfffff;
|
||||
}
|
||||
|
||||
void OPN2_PhaseGenerate(ym3438_t *chip)
|
||||
static void OPN2_PhaseGenerate(ym3438_t *chip)
|
||||
{
|
||||
Bit32u slot;
|
||||
/* Mask increment */
|
||||
slot = (chip->slot + 20) % 24;
|
||||
slot = (chip->cycles + 20) % 24;
|
||||
if (chip->pg_reset[slot])
|
||||
{
|
||||
chip->pg_inc[slot] = 0;
|
||||
}
|
||||
/* Phase step */
|
||||
slot = (chip->slot + 19) % 24;
|
||||
chip->pg_phase[slot] += chip->pg_inc[slot];
|
||||
chip->pg_phase[slot] &= 0xfffff;
|
||||
slot = (chip->cycles + 19) % 24;
|
||||
if (chip->pg_reset[slot] || chip->mode_test_21[3])
|
||||
{
|
||||
chip->pg_phase[slot] = 0;
|
||||
}
|
||||
chip->pg_phase[slot] += chip->pg_inc[slot];
|
||||
chip->pg_phase[slot] &= 0xfffff;
|
||||
}
|
||||
|
||||
void OPN2_EnvelopeSSGEG(ym3438_t *chip)
|
||||
static void OPN2_EnvelopeSSGEG(ym3438_t *chip)
|
||||
{
|
||||
Bit32u slot = chip->slot;
|
||||
Bit32u slot = chip->cycles;
|
||||
Bit8u direction = 0;
|
||||
chip->eg_ssg_pgrst_latch[slot] = 0;
|
||||
chip->eg_ssg_repeat_latch[slot] = 0;
|
||||
@@ -601,9 +603,9 @@ void OPN2_EnvelopeSSGEG(ym3438_t *chip)
|
||||
chip->eg_ssg_enable[slot] = (chip->ssg_eg[slot] >> 3) & 0x01;
|
||||
}
|
||||
|
||||
void OPN2_EnvelopeADSR(ym3438_t *chip)
|
||||
static void OPN2_EnvelopeADSR(ym3438_t *chip)
|
||||
{
|
||||
Bit32u slot = (chip->slot + 22) % 24;
|
||||
Bit32u slot = (chip->cycles + 22) % 24;
|
||||
|
||||
Bit8u nkon = chip->eg_kon_latch[slot];
|
||||
Bit8u okon = chip->eg_kon[slot];
|
||||
@@ -725,12 +727,12 @@ void OPN2_EnvelopeADSR(ym3438_t *chip)
|
||||
chip->eg_state[slot] = nextstate;
|
||||
}
|
||||
|
||||
void OPN2_EnvelopePrepare(ym3438_t *chip)
|
||||
static void OPN2_EnvelopePrepare(ym3438_t *chip)
|
||||
{
|
||||
Bit8u rate;
|
||||
Bit8u sum;
|
||||
Bit8u inc = 0;
|
||||
Bit32u slot = chip->slot;
|
||||
Bit32u slot = chip->cycles;
|
||||
Bit8u rate_sel;
|
||||
|
||||
/* Prepare increment */
|
||||
@@ -813,9 +815,9 @@ void OPN2_EnvelopePrepare(ym3438_t *chip)
|
||||
chip->eg_sl[0] = chip->sl[slot];
|
||||
}
|
||||
|
||||
void OPN2_EnvelopeGenerate(ym3438_t *chip)
|
||||
static void OPN2_EnvelopeGenerate(ym3438_t *chip)
|
||||
{
|
||||
Bit32u slot = (chip->slot + 23) % 24;
|
||||
Bit32u slot = (chip->cycles + 23) % 24;
|
||||
Bit16u level;
|
||||
|
||||
level = chip->eg_level[slot];
|
||||
@@ -846,7 +848,7 @@ void OPN2_EnvelopeGenerate(ym3438_t *chip)
|
||||
chip->eg_out[slot] = level;
|
||||
}
|
||||
|
||||
void OPN2_UpdateLFO(ym3438_t *chip)
|
||||
static void OPN2_UpdateLFO(ym3438_t *chip)
|
||||
{
|
||||
if ((chip->lfo_quotient & lfo_cycles[chip->lfo_freq]) == lfo_cycles[chip->lfo_freq])
|
||||
{
|
||||
@@ -860,14 +862,14 @@ void OPN2_UpdateLFO(ym3438_t *chip)
|
||||
chip->lfo_cnt &= chip->lfo_en;
|
||||
}
|
||||
|
||||
void OPN2_FMPrepare(ym3438_t *chip)
|
||||
static void OPN2_FMPrepare(ym3438_t *chip)
|
||||
{
|
||||
Bit32u slot = (chip->slot + 6) % 24;
|
||||
Bit32u slot = (chip->cycles + 6) % 24;
|
||||
Bit32u channel = chip->channel;
|
||||
Bit16s mod, mod1, mod2;
|
||||
Bit32u op = slot / 6;
|
||||
Bit8u connect = chip->connect[channel];
|
||||
Bit32u prevslot = (chip->slot + 18) % 24;
|
||||
Bit32u prevslot = (chip->cycles + 18) % 24;
|
||||
|
||||
/* Calculate modulation */
|
||||
mod1 = mod2 = 0;
|
||||
@@ -908,7 +910,7 @@ void OPN2_FMPrepare(ym3438_t *chip)
|
||||
}
|
||||
chip->fm_mod[slot] = mod;
|
||||
|
||||
slot = (chip->slot + 18) % 24;
|
||||
slot = (chip->cycles + 18) % 24;
|
||||
/* OP1 */
|
||||
if (slot / 6 == 0)
|
||||
{
|
||||
@@ -922,9 +924,9 @@ void OPN2_FMPrepare(ym3438_t *chip)
|
||||
}
|
||||
}
|
||||
|
||||
void OPN2_ChGenerate(ym3438_t *chip)
|
||||
static void OPN2_ChGenerate(ym3438_t *chip)
|
||||
{
|
||||
Bit32u slot = (chip->slot + 18) % 24;
|
||||
Bit32u slot = (chip->cycles + 18) % 24;
|
||||
Bit32u channel = chip->channel;
|
||||
Bit32u op = slot / 6;
|
||||
Bit32u test_dac = chip->mode_test_2c[5];
|
||||
@@ -957,16 +959,17 @@ void OPN2_ChGenerate(ym3438_t *chip)
|
||||
chip->ch_acc[channel] = sum;
|
||||
}
|
||||
|
||||
void OPN2_ChOutput(ym3438_t *chip)
|
||||
static void OPN2_ChOutput(ym3438_t *chip)
|
||||
{
|
||||
Bit32u cycles = chip->cycles;
|
||||
Bit32u slot = chip->cycles;
|
||||
Bit32u channel = chip->channel;
|
||||
Bit32u test_dac = chip->mode_test_2c[5];
|
||||
Bit16s out;
|
||||
Bit16s sign;
|
||||
Bit32u out_en;
|
||||
chip->ch_read = chip->ch_lock;
|
||||
if (chip->slot < 12)
|
||||
if (slot < 12)
|
||||
{
|
||||
/* Ch 4,5,6 */
|
||||
channel++;
|
||||
@@ -1039,9 +1042,9 @@ void OPN2_ChOutput(ym3438_t *chip)
|
||||
}
|
||||
}
|
||||
|
||||
void OPN2_FMGenerate(ym3438_t *chip)
|
||||
static void OPN2_FMGenerate(ym3438_t *chip)
|
||||
{
|
||||
Bit32u slot = (chip->slot + 19) % 24;
|
||||
Bit32u slot = (chip->cycles + 19) % 24;
|
||||
/* Calculate phase */
|
||||
Bit16u phase = (chip->fm_mod[slot] + (chip->pg_phase[slot] >> 10)) & 0x3ff;
|
||||
Bit16u quarter;
|
||||
@@ -1077,7 +1080,7 @@ void OPN2_FMGenerate(ym3438_t *chip)
|
||||
chip->fm_out[slot] = output;
|
||||
}
|
||||
|
||||
void OPN2_DoTimerA(ym3438_t *chip)
|
||||
static void OPN2_DoTimerA(ym3438_t *chip)
|
||||
{
|
||||
Bit16u time;
|
||||
Bit8u load;
|
||||
@@ -1126,7 +1129,7 @@ void OPN2_DoTimerA(ym3438_t *chip)
|
||||
chip->timer_a_cnt = time & 0x3ff;
|
||||
}
|
||||
|
||||
void OPN2_DoTimerB(ym3438_t *chip)
|
||||
static void OPN2_DoTimerB(ym3438_t *chip)
|
||||
{
|
||||
Bit16u time;
|
||||
Bit8u load;
|
||||
@@ -1171,27 +1174,29 @@ void OPN2_DoTimerB(ym3438_t *chip)
|
||||
chip->timer_b_cnt = time & 0xff;
|
||||
}
|
||||
|
||||
void OPN2_KeyOn(ym3438_t*chip)
|
||||
static void OPN2_KeyOn(ym3438_t*chip)
|
||||
{
|
||||
Bit32u slot = chip->cycles;
|
||||
Bit32u chan = chip->channel;
|
||||
/* Key On */
|
||||
chip->eg_kon_latch[chip->slot] = chip->mode_kon[chip->slot];
|
||||
chip->eg_kon_csm[chip->slot] = 0;
|
||||
chip->eg_kon_latch[slot] = chip->mode_kon[slot];
|
||||
chip->eg_kon_csm[slot] = 0;
|
||||
if (chip->channel == 2 && chip->mode_kon_csm)
|
||||
{
|
||||
/* CSM Key On */
|
||||
chip->eg_kon_latch[chip->slot] = 1;
|
||||
chip->eg_kon_csm[chip->slot] = 1;
|
||||
chip->eg_kon_latch[slot] = 1;
|
||||
chip->eg_kon_csm[slot] = 1;
|
||||
}
|
||||
if (chip->cycles == chip->mode_kon_channel)
|
||||
{
|
||||
/* OP1 */
|
||||
chip->mode_kon[chip->channel] = chip->mode_kon_operator[0];
|
||||
chip->mode_kon[chan] = chip->mode_kon_operator[0];
|
||||
/* OP2 */
|
||||
chip->mode_kon[chip->channel + 12] = chip->mode_kon_operator[1];
|
||||
chip->mode_kon[chan + 12] = chip->mode_kon_operator[1];
|
||||
/* OP3 */
|
||||
chip->mode_kon[chip->channel + 6] = chip->mode_kon_operator[2];
|
||||
chip->mode_kon[chan + 6] = chip->mode_kon_operator[2];
|
||||
/* OP4 */
|
||||
chip->mode_kon[chip->channel + 18] = chip->mode_kon_operator[3];
|
||||
chip->mode_kon[chan + 18] = chip->mode_kon_operator[3];
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1220,6 +1225,7 @@ void OPN2_SetChipType(Bit32u type)
|
||||
|
||||
void OPN2_Clock(ym3438_t *chip, Bit16s *buffer)
|
||||
{
|
||||
Bit32u slot = chip->cycles;
|
||||
chip->lfo_inc = chip->mode_test_21[1];
|
||||
chip->pg_read >>= 1;
|
||||
chip->eg_read[1] >>= 1;
|
||||
@@ -1310,7 +1316,7 @@ void OPN2_Clock(ym3438_t *chip, Bit16s *buffer)
|
||||
if (chip->mode_ch3)
|
||||
{
|
||||
/* Channel 3 special mode */
|
||||
switch (chip->slot)
|
||||
switch (slot)
|
||||
{
|
||||
case 1: /* OP1 */
|
||||
chip->pg_fnum = chip->fnum_3ch[1];
|
||||
@@ -1345,7 +1351,6 @@ void OPN2_Clock(ym3438_t *chip, Bit16s *buffer)
|
||||
OPN2_UpdateLFO(chip);
|
||||
OPN2_DoRegWrite(chip);
|
||||
chip->cycles = (chip->cycles + 1) % 24;
|
||||
chip->slot = chip->cycles;
|
||||
chip->channel = chip->cycles % 6;
|
||||
|
||||
buffer[0] = chip->mol;
|
||||
@@ -1397,6 +1402,7 @@ Bit8u OPN2_Read(ym3438_t *chip, Bit32u port)
|
||||
if (chip->mode_test_21[6])
|
||||
{
|
||||
/* Read test data */
|
||||
Bit32u slot = (chip->cycles + 18) % 24;
|
||||
Bit16u testdata = ((chip->pg_read & 0x01) << 15)
|
||||
| ((chip->eg_read[chip->mode_test_21[0]] & 0x01) << 14);
|
||||
if (chip->mode_test_2c[4])
|
||||
@@ -1405,7 +1411,7 @@ Bit8u OPN2_Read(ym3438_t *chip, Bit32u port)
|
||||
}
|
||||
else
|
||||
{
|
||||
testdata |= chip->fm_out[(chip->slot + 18) % 24] & 0x3fff;
|
||||
testdata |= chip->fm_out[slot] & 0x3fff;
|
||||
}
|
||||
if (chip->mode_test_21[7])
|
||||
{
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Alexey Khokholov (Nuke.YKT)
|
||||
* Copyright (C) 2017-2018 Alexey Khokholov (Nuke.YKT)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@@ -39,15 +39,19 @@
|
||||
* OPLx decapsulated(Matthew Gambrell, Olli Niemitalo):
|
||||
* OPL2 ROMs.
|
||||
*
|
||||
* version: 1.0.8
|
||||
* version: 1.0.9
|
||||
*/
|
||||
|
||||
#ifndef YM3438_H
|
||||
#define YM3438_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum {
|
||||
ym3438_mode_ym2612 = 0x01, /* Enables YM2612 emulation (MD1, MD2 VA2) */
|
||||
ym3438_mode_readmode = 0x02, /* Enables status read on any port (TeraDrive, MD1 VA7, MD2, etc) */
|
||||
ym3438_mode_readmode = 0x02 /* Enables status read on any port (TeraDrive, MD1 VA7, MD2, etc) */
|
||||
};
|
||||
|
||||
#include <stdint.h>
|
||||
@@ -66,7 +70,6 @@ typedef int8_t Bit8s;
|
||||
typedef struct
|
||||
{
|
||||
Bit32u cycles;
|
||||
Bit32u slot;
|
||||
Bit32u channel;
|
||||
Bit16s mol, mor;
|
||||
/* IO */
|
||||
@@ -79,7 +82,7 @@ typedef struct
|
||||
Bit8u write_busy_cnt;
|
||||
Bit8u write_fm_address;
|
||||
Bit8u write_fm_data;
|
||||
Bit8u write_fm_mode_a;
|
||||
Bit16u write_fm_mode_a;
|
||||
Bit16u address;
|
||||
Bit8u data;
|
||||
Bit8u pin_test_in;
|
||||
@@ -155,7 +158,7 @@ typedef struct
|
||||
Bit8u timer_a_load_latch;
|
||||
Bit8u timer_a_overflow_flag;
|
||||
Bit8u timer_a_overflow;
|
||||
|
||||
|
||||
Bit16u timer_b_cnt;
|
||||
Bit8u timer_b_subcnt;
|
||||
Bit16u timer_b_reg;
|
||||
@@ -166,7 +169,7 @@ typedef struct
|
||||
Bit8u timer_b_load_latch;
|
||||
Bit8u timer_b_overflow_flag;
|
||||
Bit8u timer_b_overflow;
|
||||
|
||||
|
||||
/* Register set */
|
||||
Bit8u mode_test_21[8];
|
||||
Bit8u mode_test_2c[8];
|
||||
@@ -178,7 +181,7 @@ typedef struct
|
||||
Bit8u mode_kon_csm;
|
||||
Bit8u dacen;
|
||||
Bit16s dacdata;
|
||||
|
||||
|
||||
Bit8u ks[24];
|
||||
Bit8u ar[24];
|
||||
Bit8u sr[24];
|
||||
@@ -190,7 +193,7 @@ typedef struct
|
||||
Bit8u am[24];
|
||||
Bit8u tl[24];
|
||||
Bit8u ssg_eg[24];
|
||||
|
||||
|
||||
Bit16u fnum[6];
|
||||
Bit8u block[6];
|
||||
Bit8u kcode[6];
|
||||
@@ -216,4 +219,9 @@ void OPN2_SetTestPin(ym3438_t *chip, Bit32u value);
|
||||
Bit32u OPN2_ReadTestPin(ym3438_t *chip);
|
||||
Bit32u OPN2_ReadIRQPin(ym3438_t *chip);
|
||||
Bit8u OPN2_Read(ym3438_t *chip, Bit32u port);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -28,7 +28,7 @@ typedef struct
|
||||
uint8 padtype;
|
||||
} t_input_config;
|
||||
|
||||
struct
|
||||
typedef struct
|
||||
{
|
||||
char version[16];
|
||||
uint8 hq_fm;
|
||||
@@ -62,7 +62,7 @@ struct
|
||||
uint8 lcd;
|
||||
uint8 render;
|
||||
t_input_config input[MAX_INPUTS];
|
||||
} config;
|
||||
} t_config;
|
||||
|
||||
extern char GG_ROM[256];
|
||||
extern char AR_ROM[256];
|
||||
@@ -76,6 +76,8 @@ extern char MS_BIOS_US[256];
|
||||
extern char MS_BIOS_EU[256];
|
||||
extern char MS_BIOS_JP[256];
|
||||
|
||||
extern t_config config;
|
||||
|
||||
void osd_input_update(void);
|
||||
int load_archive(char *filename, unsigned char *buffer, int maxsize, char *extension);
|
||||
extern void ROMCheatUpdate(void);
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#ifndef _S_CRC32_H
|
||||
#define _S_CRC32_H
|
||||
|
||||
static const unsigned long crc_table[256] = {
|
||||
static const unsigned int crc_table[256] = {
|
||||
0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
|
||||
0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
|
||||
0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
|
||||
@@ -61,7 +61,7 @@ static const unsigned long crc_table[256] = {
|
||||
#define DO4_CRC32(buf) DO2_CRC32(buf); DO2_CRC32(buf);
|
||||
#define DO8_CRC32(buf) DO4_CRC32(buf); DO4_CRC32(buf);
|
||||
|
||||
unsigned long crc32(unsigned long crc, const unsigned char *buf, unsigned int len)
|
||||
unsigned int crc32(unsigned int crc, const unsigned char *buf, unsigned int len)
|
||||
{
|
||||
if (buf == 0) return 0L;
|
||||
crc = crc ^ 0xffffffffL;
|
||||
|
||||
Reference in New Issue
Block a user