mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2026-05-26 13:50:37 +00:00
Neo: packed math for unsigned/signed integers (#4407)
This commit is contained in:
Marcin Mikołajczyk
committed by
GitHub
GitHub
parent
fb6502b8f1
commit
0add6b8c1f
@@ -766,7 +766,7 @@ T Translator::GetSrc64(const InstOperand& operand) {
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template IR::U64 Translator::GetSrc64<IR::U64>(const InstOperand&);
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template IR::F64 Translator::GetSrc64<IR::F64>(const InstOperand&);
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template <typename T>
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template <typename T, bool is_signed>
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pk_type<T> Translator::GetSrcPk(const InstOperand& operand) {
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constexpr bool is_float = std::is_same_v<T, IR::F32>;
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@@ -794,7 +794,8 @@ pk_type<T> Translator::GetSrcPk(const InstOperand& operand) {
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if constexpr (is_float) {
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return value;
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} else {
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return ir.BitCast<IR::U32>(value);
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return ir.BitFieldExtract(ir.BitCast<IR::U32>(value), ir.Imm32(0), ir.Imm32(16),
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is_signed);
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}
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};
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@@ -891,8 +892,9 @@ pk_type<T> Translator::GetSrcPk(const InstOperand& operand) {
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return value;
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}
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template pk_type<IR::U32> Translator::GetSrcPk<IR::U32>(const InstOperand&);
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template pk_type<IR::F32> Translator::GetSrcPk<IR::F32>(const InstOperand&);
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template pk_type<IR::U32> Translator::GetSrcPk<IR::U32, true>(const InstOperand&);
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template pk_type<IR::U32> Translator::GetSrcPk<IR::U32, false>(const InstOperand&);
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template pk_type<IR::F32> Translator::GetSrcPk<IR::F32, false>(const InstOperand&);
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void Translator::SetDst1(const InstOperand& operand, const IR::U1& value) {
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switch (operand.field) {
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@@ -1035,6 +1037,46 @@ void Translator::SetDst64(const InstOperand& operand, const IR::U64F64& value_ra
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}
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}
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template <typename T, bool is_signed>
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void Translator::SetDstPk(const InstOperand& operand, const pk_type<T>& value) {
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pk_type<T> v = value;
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if constexpr (std::is_same_v<T, IR::F32>) {
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if (operand.output_modifier.clamp) {
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v = {ir.FPSaturate(v.first), ir.FPSaturate(v.second)};
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}
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} else {
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if (operand.output_modifier.clamp) {
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if constexpr (is_signed) {
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auto lower = ir.Imm32(-32768);
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auto upper = ir.Imm32(32767);
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v = {ir.SClamp(v.first, lower, upper), ir.SClamp(v.second, lower, upper)};
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} else {
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auto imm = ir.Imm32(0xFFFF);
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v = {ir.UMin(v.first, imm), ir.UMin(v.second, imm)};
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}
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}
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}
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IR::U32 value_raw{};
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if constexpr (std::is_same_v<T, IR::F32>) {
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value_raw =
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ir.Pack2x16(AmdGpu::NumberFormat::Float, ir.CompositeConstruct(v.first, v.second));
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} else {
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value_raw = ir.Pack2x16(AmdGpu::NumberFormat::Uint,
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ir.CompositeConstruct(ir.BitCast<IR::F32, IR::U32>(v.first),
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ir.BitCast<IR::F32, IR::U32>(v.second)));
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}
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SetDst(operand, value_raw);
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}
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template void Translator::SetDstPk<IR::U32, false>(const InstOperand& operand,
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const pk_type<IR::U32>& value);
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template void Translator::SetDstPk<IR::U32, true>(const InstOperand& operand,
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const pk_type<IR::U32>& value);
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template void Translator::SetDstPk<IR::F32, false>(const InstOperand& operand,
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const pk_type<IR::F32>& value);
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void Translator::EmitFetch(const GcnInst& inst) {
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const auto code_sgpr_base = inst.src[0].code;
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@@ -292,6 +292,16 @@ public:
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void V_OR3_B32(const GcnInst& inst);
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// VOP3P
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void V_PK_MUL_LO_U16(const GcnInst& inst);
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void V_PK_ADD_I16(const GcnInst& inst);
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void V_PK_SUB_I16(const GcnInst& inst);
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void V_PK_LSHLREV_B16(const GcnInst& inst);
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void V_PK_LSHRREV_B16(const GcnInst& inst);
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void V_PK_MAD_U16(const GcnInst& inst);
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void V_PK_ADD_U16(const GcnInst& inst);
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void V_PK_SUB_U16(const GcnInst& inst);
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void V_PK_MAX_U16(const GcnInst& inst);
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void V_PK_MIN_U16(const GcnInst& inst);
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void V_PK_FMA_F16(const GcnInst& inst);
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void V_PK_ADD_F16(const GcnInst& inst);
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void V_PK_MUL_F16(const GcnInst& inst);
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@@ -345,13 +355,15 @@ private:
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template <typename T = IR::U64>
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[[nodiscard]] T GetSrc64(const InstOperand& operand);
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[[nodiscard]] IR::F32 GetSrcMix(const InstOperand& operand);
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template <typename T = IR::U32>
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template <typename T = IR::U32, bool is_signed = false>
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[[nodiscard]] pk_type<T> GetSrcPk(const InstOperand& operand);
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void SetDst1(const InstOperand& operand, const IR::U1& value);
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void SetDst(const InstOperand& operand, const IR::U32F32& value);
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template <bool is_signed = false>
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void SetDst16(const InstOperand& operand, const IR::U32F32& value);
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void SetDst64(const InstOperand& operand, const IR::U64F64& value_raw);
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template <typename T = IR::U32, bool is_signed = false>
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void SetDstPk(const InstOperand& operand, const pk_type<T>& value);
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// Vector ALU Helpers
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IR::U32 GetCarryIn(const GcnInst& inst);
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@@ -484,6 +484,26 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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return;
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// VOP3P
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case Opcode::V_PK_MUL_LO_U16:
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return V_PK_MUL_LO_U16(inst);
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case Opcode::V_PK_ADD_I16:
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return V_PK_ADD_I16(inst);
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case Opcode::V_PK_SUB_I16:
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return V_PK_SUB_I16(inst);
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case Opcode::V_PK_LSHRREV_B16:
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return V_PK_LSHRREV_B16(inst);
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case Opcode::V_PK_LSHLREV_B16:
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return V_PK_LSHLREV_B16(inst);
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case Opcode::V_PK_MAD_U16:
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return V_PK_MAD_U16(inst);
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case Opcode::V_PK_ADD_U16:
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return V_PK_ADD_U16(inst);
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case Opcode::V_PK_SUB_U16:
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return V_PK_SUB_U16(inst);
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case Opcode::V_PK_MAX_U16:
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return V_PK_MAX_U16(inst);
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case Opcode::V_PK_MIN_U16:
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return V_PK_MIN_U16(inst);
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case Opcode::V_PK_FMA_F16:
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return V_PK_FMA_F16(inst);
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case Opcode::V_PK_ADD_F16:
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@@ -1680,6 +1700,107 @@ void Translator::V_ADD3_U32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.IAdd(src0, ir.IAdd(src1, src2)));
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}
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void Translator::V_PK_MUL_LO_U16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::U32>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::U32>(inst.src[1]);
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const auto result_lo = ir.IAdd(src0.first, src1.first);
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const auto result_hi = ir.IAdd(src0.second, src1.second);
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SetDstPk<IR::U32, false>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_ADD_I16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::U32, true>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::U32, true>(inst.src[1]);
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const auto result_lo = ir.IAdd(src0.first, src1.first);
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const auto result_hi = ir.IAdd(src0.second, src1.second);
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SetDstPk<IR::U32, true>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_SUB_I16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::U32, true>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::U32, true>(inst.src[1]);
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const auto result_lo = ir.ISub(src0.first, src1.first);
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const auto result_hi = ir.ISub(src0.second, src1.second);
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SetDstPk<IR::U32, true>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_LSHLREV_B16(const GcnInst& inst) {
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const auto shift = GetSrcPk<IR::U32>(inst.src[0]);
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const auto src = GetSrcPk<IR::U32>(inst.src[1]);
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const auto result_lo = ir.ShiftLeftLogical(src.first, shift.first);
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const auto result_hi = ir.ShiftLeftLogical(src.second, shift.second);
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SetDstPk<IR::U32, false>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_LSHRREV_B16(const GcnInst& inst) {
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const auto shift = GetSrcPk<IR::U32>(inst.src[0]);
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const auto src = GetSrcPk<IR::U32>(inst.src[1]);
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const auto result_lo = ir.ShiftRightLogical(src.first, shift.first);
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const auto result_hi = ir.ShiftRightLogical(src.second, shift.second);
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SetDstPk<IR::U32, false>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_MAD_U16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::U32>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::U32>(inst.src[1]);
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const auto src2 = GetSrcPk<IR::U32>(inst.src[2]);
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const auto result_lo = ir.IAdd(ir.IMul(src0.first, src1.first), src2.first);
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const auto result_hi = ir.IAdd(ir.IMul(src0.second, src1.second), src2.second);
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SetDstPk<IR::U32, false>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_ADD_U16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::U32>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::U32>(inst.src[1]);
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const auto result_lo = ir.IAdd(src0.first, src1.first);
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const auto result_hi = ir.IAdd(src0.second, src1.second);
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SetDstPk<IR::U32, false>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_SUB_U16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::U32>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::U32>(inst.src[1]);
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const auto result_lo = ir.ISub(src0.first, src1.first);
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const auto result_hi = ir.ISub(src0.second, src1.second);
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SetDstPk<IR::U32, false>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_MAX_U16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::U32>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::U32>(inst.src[1]);
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const auto result_lo = ir.UMax(src0.first, src1.first);
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const auto result_hi = ir.UMax(src0.second, src1.second);
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SetDstPk<IR::U32, false>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_MIN_U16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::U32>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::U32>(inst.src[1]);
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const auto result_lo = ir.UMin(src0.first, src1.first);
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const auto result_hi = ir.UMin(src0.second, src1.second);
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SetDstPk<IR::U32, false>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_FMA_F16(const GcnInst& inst) {
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const auto src0 = GetSrcPk<IR::F32>(inst.src[0]);
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const auto src1 = GetSrcPk<IR::F32>(inst.src[1]);
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@@ -1688,8 +1809,7 @@ void Translator::V_PK_FMA_F16(const GcnInst& inst) {
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const auto result_lo = ir.FPFma(src0.first, src1.first, src2.first);
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const auto result_hi = ir.FPFma(src0.second, src1.second, src2.second);
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SetDst(inst.dst[0],
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ir.Pack2x16(AmdGpu::NumberFormat::Float, ir.CompositeConstruct(result_lo, result_hi)));
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SetDstPk<IR::F32>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_ADD_F16(const GcnInst& inst) {
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@@ -1699,8 +1819,7 @@ void Translator::V_PK_ADD_F16(const GcnInst& inst) {
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const auto result_lo = ir.FPAdd(src0.first, src1.first);
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const auto result_hi = ir.FPAdd(src0.second, src1.second);
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SetDst(inst.dst[0],
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ir.Pack2x16(AmdGpu::NumberFormat::Float, ir.CompositeConstruct(result_lo, result_hi)));
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SetDstPk<IR::F32>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_MUL_F16(const GcnInst& inst) {
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@@ -1710,8 +1829,7 @@ void Translator::V_PK_MUL_F16(const GcnInst& inst) {
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const auto result_lo = ir.FPMul(src0.first, src1.first);
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const auto result_hi = ir.FPMul(src0.second, src1.second);
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SetDst(inst.dst[0],
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ir.Pack2x16(AmdGpu::NumberFormat::Float, ir.CompositeConstruct(result_lo, result_hi)));
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SetDstPk<IR::F32>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_MIN_F16(const GcnInst& inst) {
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@@ -1721,8 +1839,7 @@ void Translator::V_PK_MIN_F16(const GcnInst& inst) {
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const auto result_lo = ir.FPMin(src0.first, src1.first);
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const auto result_hi = ir.FPMin(src0.second, src1.second);
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SetDst(inst.dst[0],
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ir.Pack2x16(AmdGpu::NumberFormat::Float, ir.CompositeConstruct(result_lo, result_hi)));
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SetDstPk<IR::F32>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_PK_MAX_F16(const GcnInst& inst) {
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@@ -1732,8 +1849,7 @@ void Translator::V_PK_MAX_F16(const GcnInst& inst) {
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const auto result_lo = ir.FPMax(src0.first, src1.first);
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const auto result_hi = ir.FPMax(src0.second, src1.second);
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SetDst(inst.dst[0],
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ir.Pack2x16(AmdGpu::NumberFormat::Float, ir.CompositeConstruct(result_lo, result_hi)));
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SetDstPk<IR::F32>(inst.dst[0], {result_lo, result_hi});
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}
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void Translator::V_LSHL_OR_B32(const GcnInst& inst) {
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