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Joelle van Dyne
f2a227b6d5
On a data abort, the processor will try to decode the faulting instruction so the hypervisor can emulate the read/write. However, it is not always able to do this and ISV=0 whenever the instruction is not decoded. This is the case for example if the faulting instruction is SIMD or a LDP/STP. When this happens, we can use TCG to emulate the faulting instruction. This is needed if the processor uses one of these instructions to access memory that is currently unmapped such as with VGA VRAM. Signed-off-by: Joelle van Dyne <j@getutm.app>