From 7bd7325330673e9c7ceb5f410ba8202db7fae911 Mon Sep 17 00:00:00 2001 From: Le Philousophe Date: Mon, 23 Oct 2023 05:42:37 +0000 Subject: [PATCH] MXE: Add patch to avoid emiting vmvdqa when stack is unaligned --- .../toolchain/patches/gcc-noalign.patch | 218 ++++++++++++++++++ 1 file changed, 218 insertions(+) create mode 100644 toolchains/mxe/packages/toolchain/patches/gcc-noalign.patch diff --git a/toolchains/mxe/packages/toolchain/patches/gcc-noalign.patch b/toolchains/mxe/packages/toolchain/patches/gcc-noalign.patch new file mode 100644 index 0000000..d7aaaa7 --- /dev/null +++ b/toolchains/mxe/packages/toolchain/patches/gcc-noalign.patch @@ -0,0 +1,218 @@ +commit 4eeec9367a85d390f49ebb109350ba4b90a1796c +Author: Le Philousophe +Date: Sun Oct 22 15:08:30 2023 +0200 + + Fix GCC bug #54412 + + This patch comes from https://github.com/msys2/MINGW-packages/pull/10314 + +diff --git a/plugins/gcc11/gcc11-overlay.mk b/plugins/gcc11/gcc11-overlay.mk +index 1d0937f2..4dc7f3f8 100644 +--- a/plugins/gcc11/gcc11-overlay.mk ++++ b/plugins/gcc11/gcc11-overlay.mk +@@ -32,7 +32,7 @@ $(PKG)_SUBDIR := gcc-$($(PKG)_VERSION) + $(PKG)_FILE := gcc-$($(PKG)_VERSION).tar.xz + $(PKG)_URL := https://ftp.gnu.org/gnu/gcc/gcc-$($(PKG)_VERSION)/$($(PKG)_FILE) + $(PKG)_URL_2 := https://www.mirrorservice.org/sites/sourceware.org/pub/gcc/releases/gcc-$($(PKG)_VERSION)/$($(PKG)_FILE) +-$(PKG)_PATCHES := $(dir $(lastword $(MAKEFILE_LIST)))/gcc11.patch ++$(PKG)_PATCHES := $(dir $(lastword $(MAKEFILE_LIST)))/gcc11.patch $(dir $(lastword $(MAKEFILE_LIST)))/noalign.patch + $(PKG)_DEPS := binutils mingw-w64 $(addprefix $(BUILD)~,gmp isl mpc mpfr zstd) + + _$(PKG)_CONFIGURE_OPTS = --with-zstd='$(PREFIX)/$(BUILD)' +diff --git a/plugins/gcc11/noalign.patch b/plugins/gcc11/noalign.patch +new file mode 100644 +index 00000000..94e550d7 +--- /dev/null ++++ b/plugins/gcc11/noalign.patch +@@ -0,0 +1,191 @@ ++From e3aa1d42ac5bd582fd57f40c224f3c55fc20fd69 Mon Sep 17 00:00:00 2001 ++From: Kai Tietz ++Date: Wed, 21 Apr 2021 07:54:59 +0200 ++Subject: [PATCH] add -m(no-)align-vector-insn option for i386 ++ ++--- ++ gcc/config/i386/i386-options.c | 9 +++++-- ++ gcc/config/i386/i386.opt | 8 +++++++ ++ gcc/config/i386/mingw32.h | 2 +- ++ gcc/config/i386/predicates.md | 2 +- ++ gcc/config/i386/sse.md | 43 ++++++++++++++++++++++++++++++---- ++ 5 files changed, 55 insertions(+), 9 deletions(-) ++ ++diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c ++index 91da2849c49..89333107fe4 100644 ++--- a/gcc/config/i386/i386-options.c +++++ b/gcc/config/i386/i386-options.c ++@@ -376,6 +376,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2, ++ { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY }, ++ { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT }, ++ { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS }, +++ { "-mno-align-vector-insn", MASK_NO_ALIGN_VECTOR_INSN }, ++ { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 }, ++ { "-mno-push-args", MASK_NO_PUSH_ARGS }, ++ { "-mno-red-zone", MASK_NO_RED_ZONE }, ++@@ -1074,8 +1075,12 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], ++ MASK_INLINE_STRINGOPS_DYNAMICALLY), ++ ++ IX86_ATTR_NO ("align-stringops", ++- OPT_mno_align_stringops, ++- MASK_NO_ALIGN_STRINGOPS), +++ OPT_mno_align_stringops, +++ MASK_NO_ALIGN_STRINGOPS), +++ +++ IX86_ATTR_NO ("align-vector-insn", +++ OPT_mno_align_vector_insn, +++ MASK_NO_ALIGN_VECTOR_INSN), ++ ++ IX86_ATTR_YES ("recip", ++ OPT_mrecip, ++diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt ++index c781fdc8278..549a82bcb0e 100644 ++--- a/gcc/config/i386/i386.opt +++++ b/gcc/config/i386/i386.opt ++@@ -241,6 +241,10 @@ malign-stringops ++ Target RejectNegative InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save ++ Align destination of the string operations. ++ +++malign-vector-insn +++Target RejectNegative InverseMask(NO_ALIGN_VECTOR_INSN, ALIGN_VECTOR_INSN) Save +++Use aligned vector instruction +++ ++ malign-data= ++ Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) ++ Use the given data alignment. ++@@ -416,6 +420,10 @@ mpc80 ++ Target RejectNegative ++ Set 80387 floating-point precision to 80-bit. ++ +++mno-align-vector-insn +++Target Mask(NO_ALIGN_VECTOR_INSN) Save +++Uses unaligned over aligned vector instruction memonics +++ ++ mpreferred-stack-boundary= ++ Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) ++ Attempt to keep stack aligned to this power of 2. ++diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h ++index 36e7bae5e1b..f141bb22961 100644 ++--- a/gcc/config/i386/mingw32.h +++++ b/gcc/config/i386/mingw32.h ++@@ -30,7 +30,7 @@ along with GCC; see the file COPYING3. If not see ++ #define TARGET_SUBTARGET_DEFAULT \ ++ (MASK_80387 | MASK_IEEE_FP | MASK_FLOAT_RETURNS \ ++ | MASK_STACK_PROBE | MASK_ALIGN_DOUBLE \ ++- | MASK_MS_BITFIELD_LAYOUT) +++ | MASK_MS_BITFIELD_LAYOUT | MASK_NO_ALIGN_VECTOR_INSN) ++ ++ /* See i386/crtdll.h for an alternative definition. _INTEGRAL_MAX_BITS ++ is for compatibility with native compiler. */ ++diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md ++index b1df8548af6..baca31fdf81 100644 ++--- a/gcc/config/i386/predicates.md +++++ b/gcc/config/i386/predicates.md ++@@ -1522,7 +1522,7 @@ ++ ;; less than its natural alignment. ++ (define_predicate "misaligned_operand" ++ (and (match_code "mem") ++- (match_test "MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)"))) +++ (match_test "TARGET_NO_ALIGN_VECTOR_INSN || MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)"))) ++ ++ ;; Return true if OP is a vzeroall operation, known to be a PARALLEL. ++ (define_predicate "vzeroall_operation" ++diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md ++index 9d3728d1cb0..12196a0f985 100644 ++--- a/gcc/config/i386/sse.md +++++ b/gcc/config/i386/sse.md ++@@ -1437,7 +1437,8 @@ ++ (vec_concat:V2DF (vec_select:DF (match_dup 2) ++ (parallel [(const_int 0)])) ++ (match_operand:DF 3 "memory_operand")))] ++- "TARGET_SSE2 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL +++ "TARGET_SSE2 +++ && (TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_NO_ALIGN_VECTOR_INSN) ++ && ix86_operands_ok_for_move_multiple (operands, true, DFmode)" ++ [(set (match_dup 2) (match_dup 5))] ++ "operands[5] = adjust_address (operands[1], V2DFmode, 0);") ++@@ -1448,7 +1449,8 @@ ++ (set (match_operand:V2DF 2 "sse_reg_operand") ++ (vec_concat:V2DF (match_operand:DF 4 "sse_reg_operand") ++ (match_operand:DF 3 "memory_operand")))] ++- "TARGET_SSE2 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL +++ "TARGET_SSE2 +++ && (TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_NO_ALIGN_VECTOR_INSN) ++ && REGNO (operands[4]) == REGNO (operands[2]) ++ && ix86_operands_ok_for_move_multiple (operands, true, DFmode)" ++ [(set (match_dup 2) (match_dup 5))] ++@@ -1462,7 +1464,8 @@ ++ (set (match_operand:DF 2 "memory_operand") ++ (vec_select:DF (match_operand:V2DF 3 "sse_reg_operand") ++ (parallel [(const_int 1)])))] ++- "TARGET_SSE2 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL +++ "TARGET_SSE2 +++ && (TARGET_SSE_UNALIGNED_STORE_OPTIMAL || TARGET_NO_ALIGN_VECTOR_INSN) ++ && ix86_operands_ok_for_move_multiple (operands, false, DFmode)" ++ [(set (match_dup 4) (match_dup 1))] ++ "operands[4] = adjust_address (operands[0], V2DFmode, 0);") ++@@ -8024,7 +8027,8 @@ ++ (vec_select:V2SF ++ (match_operand:V4SF 1 "nonimmediate_operand" " v,v,m") ++ (parallel [(const_int 0) (const_int 1)])))] ++- "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" +++ "TARGET_SSE && TARGET_ALIGN_VECTOR_INSN +++ && !(MEM_P (operands[0]) && MEM_P (operands[1]))" ++ "@ ++ %vmovlps\t{%1, %0|%q0, %1} ++ %vmovaps\t{%1, %0|%0, %1} ++@@ -8033,6 +8037,21 @@ ++ (set_attr "prefix" "maybe_vex") ++ (set_attr "mode" "V2SF,V4SF,V2SF")]) ++ +++(define_insn "sse_storelps_unalign" +++ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,v,v") +++ (vec_select:V2SF +++ (match_operand:V4SF 1 "nonimmediate_operand" " v,v,m") +++ (parallel [(const_int 0) (const_int 1)])))] +++ "TARGET_SSE && TARGET_NO_ALIGN_VECTOR_INSN +++ && !(MEM_P (operands[0]) && MEM_P (operands[1]))" +++ "@ +++ %vmovlps\t{%1, %0|%q0, %1} +++ %vmovups\t{%1, %0|%0, %1} +++ %vmovlps\t{%1, %d0|%d0, %q1}" +++ [(set_attr "type" "ssemov") +++ (set_attr "prefix" "maybe_vex") +++ (set_attr "mode" "V2SF,V4SF,V2SF")]) +++ ++ (define_expand "sse_loadlps_exp" ++ [(set (match_operand:V4SF 0 "nonimmediate_operand") ++ (vec_concat:V4SF ++@@ -10393,7 +10412,7 @@ ++ (vec_select:DF ++ (match_operand:V2DF 1 "nonimmediate_operand" "x,x,m") ++ (parallel [(const_int 0)])))] ++- "!TARGET_SSE2 && TARGET_SSE +++ "!TARGET_SSE2 && TARGET_SSE && TARGET_ALIGN_VECTOR_INSN ++ && !(MEM_P (operands[0]) && MEM_P (operands[1]))" ++ "@ ++ movlps\t{%1, %0|%0, %1} ++@@ -10402,6 +10421,20 @@ ++ [(set_attr "type" "ssemov") ++ (set_attr "mode" "V2SF,V4SF,V2SF")]) ++ +++(define_insn "*vec_extractv2df_0_sse_unalign" +++ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x") +++ (vec_select:DF +++ (match_operand:V2DF 1 "nonimmediate_operand" "x,x,m") +++ (parallel [(const_int 0)])))] +++ "!TARGET_SSE2 && TARGET_SSE && TARGET_NO_ALIGN_VECTOR_INSN +++ && !(MEM_P (operands[0]) && MEM_P (operands[1]))" +++ "@ +++ movlps\t{%1, %0|%0, %1} +++ movups\t{%1, %0|%0, %1} +++ movlps\t{%1, %0|%0, %q1}" +++ [(set_attr "type" "ssemov") +++ (set_attr "mode" "V2SF,V4SF,V2SF")]) +++ ++ (define_expand "sse2_loadhpd_exp" ++ [(set (match_operand:V2DF 0 "nonimmediate_operand") ++ (vec_concat:V2DF ++-- ++2.20.1 ++